Structured ASIC Composition for Multi-FPGA Behavior Matching

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Solution Overview

Problem

Existing electronic circuitry technologies, such as FPGAs, lack the ability to efficiently compose structured ASICs from multiple FPGAs while maintaining exact one-to-one behavior, leading to limitations in flexibility and performance.

Innovation Solution

The development of a methodology that composes a single structured ASIC from multiple FPGAs using interface protocols and adapters, allowing for one-to-one behavior matching by employing transport-agnostic mechanisms and CAD tools to stitch together the functionality of multiple FPGAs into a single device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple FPGAs are used to implement an electronic design, then flexibility and programming capability are improved, but device complexity and area increase

Engineering Contradiction:

ImproveflexibilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple FPGAs into a single structured ASIC device, merging their functionalities while maintaining the flexibility benefits. The composed circuitry integrates the functionality of multiple FPGAs (FPGA0, FPGA1, etc.) into one unified device, reducing system complexity while preserving adaptability through configurable logic blocks that can be programmed to match the original FPGA behavior.

Inventive Principle:

Principle #5Merging (Combining)

2Area of stationary object

If multiple FPGAs are composed into a structured ASIC, then area and latency are reduced, but maintaining exact one-to-one behavior becomes difficult

Engineering Contradiction:

ImproveareaVSAvoidbehavior matching precision

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent employs parameter changes by introducing configurable control signals and timing parameters that allow the composed circuitry to adjust its behavior to match the original FPGA system. The configurable logic blocks can be programmed with specific timing and control parameters to replicate the exact behavior of the source FPGAs, achieving precise behavioral matching while benefiting from reduced area.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If configurable logic blocks are used in FPGAs, then adaptability is improved, but area and resource usage increase

Engineering Contradiction:

Improveconfiguration capabilityVSAvoidarea

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements universal configurable logic blocks that can perform multiple functions depending on their configuration. Each logic block is designed to be multi-functional, capable of implementing various logic operations, arithmetic functions, and data path operations through programming. This universality allows the structured ASIC to achieve the same adaptability as FPGAs with reduced area, as the same hardware resources can be reconfigured for different purposes rather than requiring dedicated hardware for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8680886B1Apparatus for configurable electronic circuitry and associated methods

Publication Date: 2014.03.25 ALTERA CORP

AI summary

An apparatus for implementing an electronic design includes a structured application specific integrated circuit (ASIC). The structured ASIC includes circuitry that is adapted to implement functionality of a field programmable gate array (FPGA) that implements a part of the electronic design, as well as circuitry that is adapted to implement the functionality of at least one more FPGA that implement(s) another part (or additional parts) of the electronic design.