PLD Configuration Bitstream Alignment Using Padding Bits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for reducing the size of configuration bit streams for programmable logic devices (PLDs) are limited, leading to inefficient storage and configuration times due to the presence of 'phantom bits' that do not correspond to physical configuration elements, and compression methods vary in effectiveness depending on bit patterns.
Innovation Solution
A control block generates a new configuration bit stream by including padding bits to replace missing phantom bits, ensuring the bit stream is properly configured and aligned with physical elements, thereby reducing the size of the configuration bit stream and improving storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If compression is used to reduce configuration bit stream size, then storage space is reduced, but configuration time increases due to decompression requirement
Solution Approach 1:
The patent extracts and removes phantom bits from the configuration bit stream, eliminating unnecessary data that does not correspond to physical configuration elements. This reduction is achieved through identification and removal of redundant bits rather than compression, thus reducing storage requirements without requiring decompression operations that would increase configuration time.
2Quantity of substance
If phantom bits are removed from configuration bit stream, then bit stream size is reduced, but proper loading of Data Registers becomes problematic
Solution Approach 1:
The patent introduces a control block as an intermediary component that manages the configuration process. This control block receives the reduced configuration bit stream without phantom bits and orchestrates the proper loading of Data Registers by coordinating with Address Registers, thereby mediating between the reduced bit stream and the configuration elements to ensure correct operation.
Solution Approach 2:
The patent implements preliminary actions by having the control block read mapping information about the PLD design before configuring the device. This allows the control block to pre-determine which bits correspond to physical configuration elements and properly manage the loading process without requiring phantom bits for alignment.
3Quantity of substance
If larger memory device is used to store configuration bit stream with phantom bits, then storage capacity is sufficient, but cost and yield rate are adversely affected
Solution Approach 1:
The patent extracts and eliminates phantom bits from the configuration bit stream, reducing the total number of bits that need to be stored. This reduction allows using smaller memory devices with sufficient capacity, thereby improving manufacturing yield rates and reducing costs associated with larger memory components.
Data Source
AI summary
Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits.