Scannable Dynamic Register With Precharge for Shorter Setup Time
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Solution Overview
Problem
Dynamic logic circuits exhibit long setup and hold times, necessitating a fast dynamic register circuit with minimal setup times and scan capability without the overhead of pulsed clock circuits.
Innovation Solution
A scannable fast dynamic register is designed with a data and scan enable circuit, precharge circuit, select circuit, store circuit, and output logic gate, incorporating a data block and transistors to perform logic functions, and featuring a transparent latch configuration for efficient operation during both normal and scan modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dynamic logic circuits are used, then circuit speed is improved, but setup and hold times become long
Solution Approach 1:
The patent applies preliminary action by precharging the dynamic logic circuit before the clock edge arrives. The precharge circuit activates early to set up the necessary voltage levels and signal states, allowing the main logic operation to proceed faster without waiting for lengthy setup times. This is achieved through early activation of precharge transistors that prepare the circuit state in advance of the clock transition.
2Adaptability or versatility
If scan capability is added to dynamic logic circuits, then testability is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the scan path functionality with the existing dynamic logic circuit structure. The scan enable signal controls multiplexing between normal data input and scan input, allowing both normal operation and scan mode to share the same register hardware. This integration reduces the need for separate scan path components, thereby limiting the increase in circuit complexity while maintaining full scan capability.
Solution Approach 2:
The register circuit is designed to perform multiple functions: normal data storage during operational mode and scan chain functionality during test mode. The same register hardware responds to different control signals (normal clock vs. scan enable) to execute different operations, eliminating the need for dedicated scan-only circuits and reducing overall system complexity.
3Speed
If transparent latch configuration is used, then operation speed is improved, but interaction with dynamic circuitry increases
Solution Approach 1:
The patent segments the circuit into distinct static and dynamic portions. The transparent latch and associated control logic are implemented in static logic, isolated from the dynamic logic core by clear boundaries. This segmentation allows the transparent latch to operate at high speed without creating excessive interaction or loading effects on the dynamic circuitry, as the static portion buffers and controls the interface between the two domains.
Data Source
AI summary
A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.