Programmable I/O Buffers for Low-Power Reconfigurable Thresholds
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Solution Overview
Problem
Current reconfigurable integrated circuits lack a cost-effective method to achieve high configurability without significant power consumption and silicon real estate, limiting their ability to adapt quickly to new functional requirements.
Innovation Solution
A programmable I/O architecture that allows for configurable input/output types, drive strengths, skew, polarity, and internal resistors, enabling flexible signal conditioning and reconfiguration of I/O buffers to function as inputs, outputs, or bi-directional cells with minimal performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile memory technology (EPROM, EEPROM, OTP) is used for reconfiguration, then configurability is improved, but power consumption and silicon real estate increase significantly
Solution Approach 1:
The patent extracts the reconfiguration capability from traditional non-volatile memory implementations by using a dedicated configuration memory space within the flash memory that can be selectively programmed without affecting the entire memory array. This selective programming approach reduces the power consumption and silicon area required compared to using full non-volatile memory blocks for configuration purposes.
Solution Approach 2:
The flash memory array serves dual purposes: it functions as both the main data storage memory and as the configuration memory for reconfigurable logic. This multi-functionality eliminates the need for separate non-volatile configuration memory, thereby reducing overall power consumption and silicon real estate while maintaining high configurability.
2Adaptability or versatility
If non-volatile memory technology (EPROM, EEPROM, OTP) is used for reconfiguration, then configurability is improved, but silicon real estate increases significantly
Solution Approach 1:
The flash memory array serves dual purposes: it functions as both the main data storage memory and as the configuration memory for reconfigurable logic. This multi-functionality eliminates the need for separate non-volatile configuration memory, thereby reducing overall power consumption and silicon area while maintaining high configurability.
Solution Approach 2:
The patent merges the configuration memory function with the main data storage memory by using the same flash memory array for both purposes. This consolidation integrates multiple functions into a single memory structure, significantly reducing the silicon area required compared to having separate configuration and data storage memory blocks.
3Adaptability or versatility
If traditional reconfigurable architectures (masked ROM, gate-arrays, analog arrays) are used, then adaptability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent replaces traditional mechanical and physical reconfiguration methods (masked ROM, gate-arrays, analog arrays requiring wafer fabrication reticle changes) with an electrical programming approach using flash memory. This substitution allows reconfiguration through software-like programming rather than physical manufacturing changes, significantly simplifying the manufacturing process while maintaining high adaptability.
Solution Approach 2:
The system enables dynamic reconfiguration of logic functions and memory array characteristics through electrical programming of the flash memory, allowing the circuit to adapt its behavior after manufacturing without requiring complex reconfigurable hardware structures. This dynamic adaptability is achieved through software-controlled configuration rather than physical reconfiguration mechanisms.
Data Source
AI summary
A buffer device coupled to at least one input/output port of an integrated circuit has a plurality of control inputs configured to receive configuration programming information. The at least one input/output circuit is capable of: (a) being configured in a directional sense of communication by the configuration programming information, (b) being configured as an input circuit which can be further configured to provide input logic switching level thresholds according to the configuration programming information, and (c) being configured as at least one output circuit which can be further configured to provide an output drive strength according to the configuration programming information.