3D IC Clock Distribution and Scan Chain Testing Structure
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Solution Overview
Problem
The development of true three-dimensional integrated circuits (3D ICs) faces challenges in yield and reliability due to complex architectures and the need for new manufacturing techniques, particularly in deep submicron process generations, where existing testing methods are not adequately effective.
Innovation Solution
The implementation of a 3D device architecture with aligned layers, featuring a first layer with interconnected transistors and a second layer with overlaying transistors, including a clock distribution structure and flip-flops forming a scan chain, along with programmable interconnect tiles using antifuse technology, allows for enhanced connectivity and testing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through Silicon Via technology is used to bond multiple layers of silicon to form true 3D ICs, then device integration and functionality are improved, but yield and reliability deteriorate due to manufacturing complexity
Solution Approach 1:
The patent divides the monolithic 3D IC structure into separate bonded layers (first semiconductor layer and second semiconductor layer) connected through Through Silicon Vias. This segmentation allows independent fabrication and testing of each layer before bonding, improving yield by isolating defects to specific layers rather than requiring perfect integration across the entire structure.
Solution Approach 2:
The patent implements preliminary testing and characterization of each semiconductor layer independently before bonding them together. Scan chains are configured in each layer prior to bonding, allowing defects to be detected and isolated before the bonding process, thereby improving overall yield and reliability by preventing propagation of defects through the bonding interface.
2Adaptability or versatility
If complex architectures are implemented in 3D ICs, then functionality and performance are improved, but manufacturing difficulty and cost increase
Solution Approach 1:
The patent segments the complex 3D IC architecture into standardized modular layers that can be independently manufactured using standard CMOS processes. Each layer contains functional blocks interconnected through Through Silicon Vias, allowing complex functionality to be achieved through stacking simple, well-understood manufacturing steps rather than requiring new complex processes.
Solution Approach 2:
The patent creates universal interface structures and Through Silicon Via patterns that can be used across different layer configurations and device types. This standardization allows the same manufacturing processes to produce various 3D IC architectures with different functionalities, reducing manufacturing difficulty by reusing proven processes rather than developing new ones for each application.
3Productivity
If existing testing methods are applied to 3D ICs, then test infrastructure is maintained, but testing effectiveness deteriorates due to architectural differences
Solution Approach 1:
The patent extends traditional 2D scan chain testing into the third dimension by configuring scan chains that traverse through multiple bonded layers via Through Silicon Vias. This dimensional extension allows existing testing infrastructure to effectively test 3D architectures by adding vertical connectivity to the scan chain paths, maintaining compatibility with current testers while achieving comprehensive 3D coverage.
Solution Approach 2:
The patent introduces intermediate testing structures at the bonding interfaces between layers, including test vias and intermediate scan chain segments. These intermediaries act as mediators that allow test signals to propagate through the bonded structure and enable defect detection at critical interfaces without requiring complete redesign of the testing infrastructure.
4Manufacturing precision
If aligned layer architecture is implemented with clock distribution structures, then clock synchronization is improved, but device complexity increases
Solution Approach 1:
The patent merges the clock distribution function with the existing Through Silicon Via structure by routing clock signals through the same vertical interconnects used for data transmission. This consolidation eliminates the need for separate clock distribution pathways, reducing device complexity while maintaining precise clock synchronization across bonded layers through the aligned layer architecture.
Data Source
AI summary
A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.