3D IC Stacking Using SiGe Sacrificial Layer Transfer

The patent transitions from 2D planar integration to 3D vertical stacking, arranging transistor layers and wire layers in different spatial dimensions. This allows transistors to be positioned directly above/below each other, dramatically reducing wire lengths and improving wire performance while maintaining high transistor density.

The patent implements a nested structure where multiple transistor layers are stacked vertically with wire layers interspersed between them. Each layer is contained within the vertical stack, creating a compact 3D integrated circuit where transistors and wires coexist in a nested hierarchical arrangement.

The patent segments the 3D stack into distinct functional layers (transistor layers, wire layers, isolation layers) separated by thermal isolation structures. This segmentation allows heat from active transistor regions to be managed independently from wire regions, improving thermal isolation despite the compact 3D arrangement.

The patent introduces thermal isolation layers and materials as intermediary structures between transistor layers and wire layers. These intermediary layers act as thermal barriers, preventing heat transfer between adjacent layers while allowing electrical and mechanical integration.

The patent performs preliminary actions by forming through-silicon vias (TSVs) and bonding interfaces on donor wafers before the actual layer transfer process. This preliminary preparation ensures that when layers are transferred and stacked, the bonding occurs efficiently with proper alignment and mechanical strength.

The patent uses TSVs and bonding layers as intermediary structures that facilitate the transfer and integration of heterogeneous layers. These intermediaries enable mechanical support, electrical connection, and thermal management during the layer transfer and stacking process.