3D IC Placement Across Strata for Dense Inter-Layer Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CAD tools struggle to optimize the placement and routing of transistors in monolithic 3D integrated circuits, as inter-layer connectivity is denser and requires leveraging the potentially disparate characteristics of different layers to increase physical proximity, unlike in 2D planes.
Innovation Solution
The method involves using 2D placers and routers to optimize the placement and routing of transistors across multiple strata in monolithic 3D integrated circuits, considering the unique characteristics of each layer, such as lithography requirements and process costs, to enhance connectivity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing CAD tools are used for 2D placement and routing, then the design process is simple and well-established, but the tools cannot optimize the dense inter-layer connectivity in monolithic 3D integrated circuits
Solution Approach 1:
The patent extends traditional 2D placement and routing algorithms into the third dimension by introducing strata-based organization. Cells are assigned to different strata (layers) and the placer optimizes both horizontal positioning within strata and vertical positioning across strata, enabling effective utilization of dense inter-layer connectivity in monolithic 3D ICs while maintaining compatibility with existing CAD tool frameworks
2Manufacturing precision
If manual placement and routing optimization is performed, then design precision can be improved, but the design time and productivity decrease significantly
Solution Approach 1:
The patent implements automated placement optimization algorithms that self-adjust cell positions across multiple strata based on connectivity requirements and design constraints. The system automatically evaluates placement quality metrics and performs iterative optimization without manual intervention, achieving high placement precision while maintaining design efficiency through computer-aided automation
Solution Approach 2:
The placer incorporates feedback mechanisms that continuously evaluate placement quality based on inter-layer connectivity metrics, timing constraints, and design rules. The algorithm uses this feedback to iteratively improve cell positioning across strata, automatically converging to optimized placements that maximize the benefits of 3D monolithic architecture
Data Source
AI summary
A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors and is disposed on top of the first level; levels connection pads (LCPs) disposed between the first level and second level; providing placement of the LCPs; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement of the LCPs, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool.