Computer Aided Design TRIZ Cases
- Circuit Timing Tradeoff Using Slack-Based Area and Power Thresholds
Local timing data sets area and power sacrifice thresholds so EDA transforms improve slack where needed without unnecessary circuit overhead.
- PCB Component Layout With Central Switches for Signal Integrity
Parallel processing nodes, central interconnect switches, and edge microcontrollers improve PCB signal integrity, latency, and communication speed.
- Backside Power Mesh Layout for Low-RC Semiconductor Rails
Routing power rails beneath semiconductor cells expands routing area, cuts resistance and capacitance, and improves interconnect reliability.
- IC Pattern Layout With Mandrel Bars for Lithography Accuracy
Dummy patterns and mandrel bars raise IC pattern density and prevent space violations that degrade lithography accuracy at smaller nodes.
- Floating Gate IC Layout for Routing and Area Optimization
Replacing selected dummy gate isolation and removing redundant vias frees routing space, cuts area use, and improves IC speed.
- Dual-Port Memory Cell Stacking for Two Accesses Per Clock
Alternating pass-gate levels and bit lines on opposite substrate sides shrink memory cell area while enabling two accesses per clock cycle.
- Logic Cell Noise Tolerance Curves for False Violation Reduction
Multiple noise tolerance curves matched to logic-cell capacitive load cut false noise violations and improve EDA verification efficiency.
- VLSI Cell Distribution Estimation for Early Power Assessment
A neural-network estimator predicts VLSI cell distribution from characterization data, cutting APR turn-around for earlier power and leakage assessment.
- Substrate Recipe Simulation for Processing Step Effect Visualization
Simulation compares substrate recipes and predicted shapes to reveal how step changes affect results, reducing trial-and-error tuning.
- Synthesized Logic Equivalence Checking via Synthesis History Replay
Stored synthesis history is replayed to verify optimized arithmetic logic against the high-level design without exponential equivalence checking runtime.
- 3D IC Placement Across Strata for Dense Inter-Layer Routing
Using 2D CAD placers and routers across stacked strata improves monolithic 3D IC placement, inter-layer connectivity, and design efficiency.
- Pixel Circuit Layout for Close Transistor-Capacitor Placement
Constraint-based pixel circuit layout places transistors and capacitors closer to cut parasitic capacitance, noise, and manual design time.
- Potential Fix Cell Layout for Spare Cell Spacing Control
A boundary-wired potential fix cell lets spare cell inputs be fixed from upper layers while suppressing spacing errors and easing design changes.
- Content Compute Processor Architecture for Reconfigurable Hardware Execution
A Syn-Compiler maps high-level code into reconfigurable hardware instructions to ease FPGA-style configuration and raise IPC.
- Integrated Circuit Cell Layout With 1.5-Row Standard Cells
Using 1.5-row and 1-row cells with dummy regions, this layout improves IC packing density while limiting leakage and transition-related process issues.
- IC Standard Cell Layout with APR Pin Reconnection
APR connects grouped disconnected pins in non-functional standard cells, improving IC layout flexibility and specification compliance.
- Post-Silicon ASIC Layout Recovery for DRC-Based Verification
Open-source delayering, extraction, and synthetic DRC rules rebuild ASIC layouts for more accurate post-silicon verification.
- Hybrid Nano-Sheet Integrated Circuit with Back-Side Power Vias
Back-side vias move power connections away from the front side, freeing area for wider active sheets and more flexible IC layouts.