Logic Cell Noise Tolerance Curves for False Violation Reduction
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Solution Overview
Problem
Existing electronic design automation tools face challenges in accurately predicting circuit behavior due to overly pessimistic noise tolerance analysis, leading to false failures and inefficiencies in circuit design, particularly in very large scale integrated circuits.
Innovation Solution
Adaptive noise tolerance design processing that adjusts capacitive loads on logic cell instances using antenna diodes to match selected noise tolerance data curves, reducing pessimistic noise analysis and minimizing circuit disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional noise tolerance analysis is used, then circuit design verification is performed, but false noise violations occur leading to pessimistic results
Solution Approach 1:
The patent applies preliminary action by pre-characterizing logic cells with multiple noise tolerance data curves corresponding to different capacitive loads before actual circuit verification. This allows the EDA tool to select the appropriate curve in advance based on the actual capacitive load, avoiding the need for conservative worst-case assumptions during verification and eliminating false noise violations.
Solution Approach 2:
The patent implements parameter changes by transitioning from a single fixed noise tolerance curve to multiple noise tolerance data curves, each corresponding to a specific capacitive load parameter. The system dynamically selects and applies the appropriate curve based on the actual capacitive load of the logic cell instance, thereby achieving accurate noise tolerance analysis without pessimistic false violations.
2Object-affected harmful factors
If conservative noise analysis is applied, then noise violations are detected, but circuit design productivity decreases due to false failures
Solution Approach 1:
The patent applies local quality by tailoring the noise tolerance analysis to the specific local conditions of each logic cell instance. Instead of applying a uniform conservative noise margin to all cells, the system determines the actual capacitive load for each cell and selects the corresponding noise tolerance data curve, providing locally optimized noise verification that reduces false violations and improves productivity.
3Measurement precision
If multiple noise tolerance data curves are used, then accurate noise analysis is achieved, but device complexity increases
Solution Approach 1:
The patent manages the complexity of multiple noise tolerance data curves through preliminary action by pre-characterizing logic cells during library preparation. The multiple curves are pre-computed and stored in the logic cell library, so that during circuit verification, the EDA tool only needs to determine the actual capacitive load and select the corresponding pre-prepared curve, avoiding the complexity of real-time multiple curve management.
4Reliability
If capacitive load is adjusted to match noise tolerance curves, then false violations are reduced, but additional circuit elements are required
Solution Approach 1:
The patent applies copying by using capacitive load modeling rather than physical capacitance elements. The EDA tool creates a logical copy or representation of the capacitive load based on the actual circuit connections and parameters, allowing the selection of the appropriate noise tolerance data curve without adding physical capacitors or other circuit elements to the design.
Data Source
AI summary
A circuit design process is provided which includes performing noise impact on function testing of an instance of a logic cell within a circuit design, and based on the logic cell instance failing the noise impact on function testing, addressing the failure of the logic cell instance. The addressing includes selecting a noise tolerance data curve of multiple noise tolerance data curves with different associated capacitive loads on the logic cell, and adjusting an effective capacitive load on the logic cell instance to obtain an adjusted capacitive load corresponding to the associated capacitive load of the selected noise tolerance data curve. Further, the addressing includes verifying that the logic cell instance passes noise impact on function testing based on comparing a noise pulse at the logic cell instance to the selected noise tolerance data curve.