Potential Fix Cell Layout for Spare Cell Spacing Control
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Solution Overview
Problem
In semiconductor device design changes, disconnecting power supply and input wirings of spare cells to prevent through-currents leads to a high risk of spacing errors between output and adjacent cell wirings, especially when the output wiring is pulled up to an upper layer.
Innovation Solution
A potential fix cell is introduced with output wirings in upper layers connected to power supply potentials, arranged at cell boundaries to suppress spacing errors by maintaining adequate distance from adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the output wiring is pulled up to an upper layer to reduce manufacturing cost for design changes, then the ease of manufacture is improved, but the spacing error between output wiring and adjacent cell wirings increases
Solution Approach 1:
The patent applies dimensionality change by transitioning the output wiring from a two-dimensional planar arrangement to a three-dimensional multi-layer structure. The output wiring is pulled up to an upper layer (metal layer 2 or higher) while the power supply wiring remains in the lower layer (metal layer 0), creating vertical separation that resolves the spacing conflict and enables easier design modifications in upper layers without affecting adjacent cells.
Solution Approach 2:
The patent segments the wiring structure into distinct layers with different functions. The power supply wiring is confined to the lower layer (metal layer 0) at cell boundaries, while the output wiring is separated and placed in upper layers. This segmentation allows independent optimization of each wiring type, enabling design changes to output wirings without impacting power supply connections or adjacent cells.
2Reliability
If the power supply wiring and input wiring are disconnected to prevent through-current, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent introduces a potential fix cell as an intermediary component between the power supply wiring and the spare cell input wiring. This potential fix cell includes a transistor that actively controls the potential of the input wiring, preventing through-current flow while maintaining a simple wiring topology. The intermediary device resolves the contradiction by providing reliable isolation without requiring complex wiring disconnections.
Data Source
AI summary
A semiconductor device includes: a logical cell; a spare cell; and a potential fix cell outputting a reference potential used for fixing a potential of an input wiring of the spare cell. The potential fix cell includes: a mutual connection wiring; a first wiring; a second wiring; and an output wiring. The second wiring has a power supply potential, and is wired at a cell boundary between the potential fix cell and an adjacent different cell. The first wiring is wired inside the potential fix cell. The output wiring outputs the reference potential in response to reception of the power supply potential through the second wiring, the mutual connection wiring and the first wiring.