IC Standard Cell Layout with APR Pin Reconnection
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in ensuring that standard cell layout designs meet strict specifications and maintain functionality, as non-functional circuits often result from disconnected pins within standard cells.
Innovation Solution
A method involving automatic placement and routing (APR) tools to connect disconnected pins in non-functional circuits, transforming them into functional circuits by designating specific pins as a group to be connected, thereby enhancing the flexibility of the layout design and manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If standard cell layout designs are miniaturized to reduce device size and power consumption, then device functionality and integration density are improved, but manufacturing precision and design verification become more difficult due to stricter specifications and potential pin disconnections
Solution Approach 1:
The system performs preliminary verification of pin connections and circuit functionality during the automated placement and routing stage, before manufacturing. The EDA tool checks whether pins are properly connected and circuits are functional, identifying issues early in the design process rather than during manufacturing, thus preventing defects in miniaturized layouts
Solution Approach 2:
The system implements feedback mechanisms where the EDA tool continuously monitors and verifies pin connections and circuit functionality during automated placement and routing. When disconnections or non-functional circuits are detected, the system provides feedback to adjust the layout, ensuring compliance with manufacturing specifications even as device size decreases
2Productivity
If automated placement and routing tools are used to increase design efficiency and productivity, then manufacturing speed is improved, but the complexity of ensuring proper pin connections and circuit functionality increases
Solution Approach 1:
The EDA tool performs self-verification of pin connections and circuit functionality during the automated placement and routing process. The system automatically checks whether pins are connected and circuits are functional without requiring additional manual intervention, thus maintaining high productivity while managing verification complexity
Solution Approach 2:
The EDA tool is designed to perform multiple functions simultaneously: automated placement, routing, pin connection verification, and circuit functionality checking. This multi-functionality consolidates complex verification tasks into a single integrated process, maintaining design efficiency while ensuring proper connections in miniaturized circuits
3Adaptability or versatility
If pins are disconnected in non-functional circuits during layout design, then layout flexibility is improved, but circuit functionality is lost
Solution Approach 1:
The EDA tool implements feedback verification to detect when pin disconnections result in non-functional circuits. When such issues are identified, the system provides feedback to adjust the layout, ensuring that pins are properly connected while maintaining layout flexibility for miniaturized designs
Solution Approach 2:
The system performs preliminary verification of circuit functionality during the layout design stage, before manufacturing. By checking whether disconnected pins result in non-functional circuits early in the design process, the system prevents functionality loss while maintaining layout flexibility
Data Source
AI summary
A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, and placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit, and includes a first and second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes labelling the first and second pin as a first set of to be connected pins, and designating the first set of to be connected pins as a common group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first set of to be connected pins in the common group of pins together, thereby changing the first circuit to a second circuit.