Dual-Port Memory Cell Stacking for Two Accesses Per Clock
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines affects operating voltages and overall IC performance, necessitating a solution to optimize memory cell design for reduced area occupation and improved functionality.
Innovation Solution
A dual-port memory cell design is implemented with pass-gate transistors of different types on alternating levels, separated by gate isolation layers to minimize area usage while maintaining functionality, utilizing a first and second port configuration with word lines on opposite sides of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory cell design is used, then area occupation is larger, but functionality and access efficiency are limited
Solution Approach 1:
The patent implements a dual-port memory cell design that utilizes three-dimensional spatial arrangement by placing word lines on opposite sides of the substrate and configuring pass-gate transistors on alternating levels. This vertical stacking approach enables simultaneous access to the same memory cell through two different ports, effectively doubling the access throughput without proportionally increasing the planar area occupation.
Solution Approach 2:
The memory cell is segmented into two independent ports, each with its own pair of bit lines and control structures. The first port includes first and second bit lines with associated pass-gate transistors, while the second port includes third and fourth bit lines with separate pass-gate transistors. This segmentation allows parallel operation of both ports, enabling simultaneous read or write operations without interference.
2Area of stationary object
If IC size is reduced, then integration density improves, but conductive line resistance increases affecting performance
Solution Approach 1:
The patent employs selective doping regions with different electrical characteristics in different areas of the memory cell. Specifically, first and second doping regions are formed with first electrical characteristics, while third and fourth doping regions are formed with second electrical characteristics. This local differentiation optimizes the electrical performance of conductive paths in each region, compensating for the increased resistance that would normally result from miniaturization.
Data Source
AI summary
A dual-port memory cell (DPMC) includes a first, second, third, and fourth pass-gate transistor, and a first and a second bit line. The first pass-gate transistor includes a first gate on a first level. The second pass-gate transistor includes a second gate on a second level below the first level. The third pass-gate transistor includes a third gate on the first level. The fourth pass-gate transistor includes a fourth gate on the second level. The first bit line is on a first metal layer above a front-side of a substrate, and is coupled to the first pass-gate transistor. The second bit line is on a second metal layer below a back-side of the substrate, and is coupled to the second pass-gate transistor. The first and third pass-gate transistor correspond to a first port of the DPMC. The second and fourth pass-gate transistor correspond to a second port of the DPMC.