Pixel Circuit Layout for Close Transistor-Capacitor Placement

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Solution Overview

Problem

Existing technologies struggle to automatically generate optimal layout data for analog circuits in pixel circuits, particularly in display devices, due to layout limitations that affect display quality, signal delay, and parasitic capacitance, necessitating manual design by experienced personnel.

Innovation Solution

A circuit layout generation system incorporating a memory portion, limitation data arithmetic portion, and layout data arithmetic portion to generate layout data based on circuit connection and limitation data, optimizing transistor and capacitor placement to reduce parasitic capacitance and signal noise, thereby improving display quality and reducing design time and labor costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If manual design methods are used by experienced personnel, then layout quality and display performance are improved, but design time and labor costs increase

Engineering Contradiction:

Improvelayout qualityVSAvoiddesign time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The system enables automatic generation of layout data through arithmetic processing, allowing the computer to perform tasks traditionally requiring human expertise. The limitation data arithmetic portion and layout data arithmetic portion work autonomously to optimize transistor and capacitor placement without continuous human intervention, reducing both time and labor costs while maintaining quality through algorithmic optimization

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The system transforms qualitative design expertise into quantitative parameters through limitation data. By converting design rules and quality criteria into mathematical constraints (limitation data), the system enables automated arithmetic processing to optimize layout parameters, achieving both speed and quality through parameter-based optimization

Inventive Principle:

Principle #35Parameter changes

2Productivity

If automatic generation is attempted without sufficient limitation conditions, then design time is reduced, but layout quality and display performance deteriorate

Engineering Contradiction:

Improvedesign efficiencyVSAvoidlayout quality

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The system performs preliminary action by pre-defining comprehensive limitation data that encodes all necessary design rules and quality criteria before the automatic layout generation process begins. This preliminary preparation of constraints ensures that the subsequent automated arithmetic processing can efficiently find optimal solutions without compromising quality, as all quality requirements are already embedded in the limitation data

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses feedback mechanisms where the limitation data arithmetic portion continuously refines layout candidates based on evaluated performance against stored limitation conditions. The iterative process provides feedback loops that guide the optimization toward high-quality solutions, ensuring both speed and quality are achieved through guided search rather than random generation

Inventive Principle:

Principle #23Feedback

3Manufacturing precision

If comprehensive limitation conditions are added to ensure quality, then layout optimization is improved, but computational complexity increases

Engineering Contradiction:

Improvelayout optimizationVSAvoidcomputational complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The system segments the complex computational task into distinct functional portions: the limitation data arithmetic portion handles constraint management separately from the layout data arithmetic portion that performs optimization. This segmentation allows comprehensive limitation conditions to be organized and processed systematically, reducing computational complexity through modular architecture while maintaining thorough optimization

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system transforms complex qualitative design considerations into standardized quantitative parameters in the limitation data. By converting diverse quality requirements into uniform mathematical constraints, the system enables efficient arithmetic processing even with comprehensive conditions, reducing computational complexity through parameter standardization

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12475292B2Circuit layout generation system

Publication Date: 2025.11.18 SEMICON ENERGY LAB CO LTD

AI summary

The circuit layout generation system includes a memory portion, a limitation data arithmetic portion, and a layout data arithmetic portion. The memory portion is configured to store circuit connection data and first limitation data. The circuit connection data is data regarding connection of a transistor and a capacitor included in a pixel circuit. The first limitation data includes data that determines a wiring interval of the transistor and a wiring interval of the capacitor and data that determines placement coordinates of the transistor and the capacitor. The limitation data arithmetic portion is configured to generate second limitation data on the basis of the circuit connection data and the first limitation data and store the second limitation data in the memory portion. The second limitation data is data that determines the placement of the transistor and the capacitor designated by the placement coordinates so that the transistor and the capacitor are positioned close to each other. The layout data arithmetic portion is configured to generate layout data on the basis of the circuit connection data, the first limitation data, and the second limitation data.