Post-Silicon ASIC Layout Recovery for DRC-Based Verification
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Solution Overview
Problem
ASIC design flow faces challenges in post-manufacturing verification and validation due to the inability to alter functionality or fix bugs, leading to potential security threats and reputation risks, especially in fabless design processes where there is a disconnect between design and manufacturing.
Innovation Solution
Utilizing open-source tools and DRC rules on post-silicon layouts to perform delayering, device extraction, and rectilinearization, creating a synthetic DRC deck to correct and align shapes, and derive a netlist for accurate verification and validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ASIC design flow uses traditional closed-source tools and processes, then manufacturing precision and reliability are maintained through proprietary control, but flexibility and adaptability for post-manufacturing verification are reduced
Solution Approach 1:
The patent creates a digital copy of the physical ASIC layout by delayering the manufactured chip and reconstructing the layout geometry. This copy enables verification without modifying the actual device, maintaining reliability while allowing extensive analysis and adaptation for different verification scenarios.
Solution Approach 2:
The patent introduces an intermediary process layer that translates between the physical manufactured layout and the design verification requirements. This intermediary enables accurate verification by bridging the gap between fabrication reality and design specifications without requiring changes to either the manufacturing process or the verification tools.
2Reliability
If ASIC design flow implements comprehensive verification processes, then reliability and bug detection improve, but time consumption and complexity increase
Solution Approach 1:
The patent performs preliminary delayering and layout reconstruction before verification begins. By preparing the digital layout copy in advance with accurate geometric information, the actual verification process can proceed more quickly without needing to perform time-consuming measurements during verification.
Solution Approach 2:
The patent replaces manual measurement and verification methods with automated computational processes. The delayering and layout extraction are performed through automated image processing and geometric reconstruction algorithms, significantly reducing the time required compared to manual verification techniques.
3Adaptability or versatility
If ASIC design flow uses open-source tools for delayering and layout extraction, then adaptability and cost-effectiveness improve, but manufacturing precision and measurement accuracy may deteriorate
Solution Approach 1:
The patent adjusts the parameters and settings of open-source tools to optimize them for high-precision layout extraction. By carefully tuning parameters such as image processing thresholds, geometric reconstruction algorithms, and measurement tolerances, the system achieves accurate extraction while maintaining the adaptability benefits of open-source tools.
4Measurement precision
If ASIC design flow performs detailed layout analysis and rectilinearization, then verification accuracy improves, but device complexity and processing requirements increase
Solution Approach 1:
The patent divides the layout analysis process into distinct segments: delayering individual metal layers, extracting geometric features, performing rectilinearization separately, and finally comparing with reference layouts. This segmentation allows each step to be optimized independently and reduces the complexity of any single processing stage.
Data Source
AI summary
In an approach to generating a DRC clean design, a method includes generating successive images of an integrated circuit, each of the successive images being associated with a different one of a plurality of layers of the integrated circuit; determining a layout of the integrated circuit in response to the successive images; collecting at least one measurement of at least one feature in the layout; and modifying the layout in response to the at least one measurement.