Backside Power Mesh Layout for Low-RC Semiconductor Rails
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Solution Overview
Problem
As semiconductor devices shrink in size, the resistance and capacitance of power rails increase, leading to deteriorating device performance and manufacturing challenges such as high yield loss and reduced reliability of electrical interconnections.
Innovation Solution
Implementing a backside power rail scheme where power rails are routed beneath the cells, enlarging the routing area and reducing resistance and capacitance, while maintaining or improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are miniaturized to increase functional density, then the number of interconnected devices per chip area increases, but the resistance and capacitance of power rails increase leading to deteriorating device performance
Solution Approach 1:
The patent introduces a backside power rail layer beneath the substrate, adding a new spatial dimension for power distribution. This allows power rails to be routed in the vertical dimension (below the substrate) rather than only in the horizontal plane, effectively increasing the routing area without occupying additional chip area and reducing resistance and capacitance effects
Solution Approach 2:
The power distribution system is segmented into multiple layers: front-side power rails above the substrate and backside power rails below the substrate. This segmentation allows independent optimization of each layer's routing paths, enabling shorter and more efficient power delivery paths that reduce resistance and capacitance
2Length of moving object
If device size is reduced, then geometric size decreases, but manufacturing complexity increases causing high yield loss and reduced reliability of electrical interconnection
Solution Approach 1:
By moving power rail routing to the backside of the substrate, the patent simplifies front-side manufacturing processes. The backside power rails can be formed using separate processing steps that do not interfere with front-side device fabrication, reducing manufacturing complexity and yield loss
3Area of stationary object
If power rails are routed only on the front side of cells, then routing area is limited, but resistance and capacitance increase deteriorating performance
Solution Approach 1:
The patent utilizes the vertical dimension by routing power rails on both the front side and backside of the substrate. This effectively doubles the available routing area for power distribution, allowing for shorter and more numerous power delivery paths that reduce resistance and capacitance effects
Solution Approach 2:
The patent merges front-side and backside power rail systems into a unified three-dimensional power distribution network. This combination allows power to be delivered through multiple parallel paths, reducing overall resistance and improving electrical interconnection reliability
Data Source
AI summary
A semiconductor structure includes: a doped region extending in a first direction; a first gate structure extending in a second direction over the doped region; a first source/drain region on a first side of the doped region; a first power rail over an upper surface of the first source/drain region and electrically connected to the first source/drain region; and a second power rail below a lower surface of the first source/drain region and electrically connected to the first source/drain region. The first power rail overlaps the second power rail from a top-view perspective