VLSI Cell Distribution Estimation for Early Power Assessment
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently estimating power consumption and leakage power values during the advanced manufacturing node, particularly due to the long turn-around times and immaturity of Automatic Placement and Routing (APR) tools, necessitating a more efficient method for evaluating Very Large Scale Integration (VLSI) cell distribution.
Innovation Solution
A method involving data cleaning, characterization engineering, and model training using a deep neural network to estimate Very Large Scale Integration (VLSI) cell distribution, allowing for early assessment of power metrics in semiconductor devices, leveraging existing design databases and VLSI libraries to reduce storage usage and commercial licenses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Automatic Placement and Routing (APR) tools are used for VLSI cell distribution estimation, then manufacturing decisions can be made, but the turn-around time becomes excessively long and the tools remain immature
Solution Approach 1:
The patent creates a simplified copy of the complex APR tool functionality by training a neural network model on APR tool outputs. This model copy can rapidly estimate VLSI cell distribution and power metrics without requiring the full APR tool execution, thus reducing turn-around time while maintaining decision-making capability
Solution Approach 2:
The patent performs preliminary characterization engineering to extract key features and train the neural network model before actual manufacturing decisions are needed. This preliminary action creates a ready-to-use estimation system that eliminates the need for time-consuming APR tool execution during the decision-making process
2Measurement precision
If comprehensive VLSI cell distribution data is stored for model training, then estimation accuracy improves, but storage requirements increase significantly
Solution Approach 1:
The patent extracts only the most critical features and characteristics from the comprehensive VLSI cell distribution data during characterization engineering. Instead of storing and processing all raw data, the system identifies and retains only the essential features needed for accurate estimation, significantly reducing storage requirements while maintaining model accuracy
Solution Approach 2:
The patent applies different processing and storage quality levels to different portions of the data. Critical features that most impact estimation accuracy are retained in high detail, while less important data is aggregated or discarded, creating an optimized data structure that balances accuracy with storage efficiency
Data Source
AI summary
A method includes: generating a distribution pattern according to driving sizes of logic gates of a first semiconductor device corresponding to first data; transforming the distribution pattern to distribution data; generating first characterization data of the first semiconductor device according to the first data; generating first estimated distribution data according to the first characterization data by a model; training the model according to the first estimated distribution data and the distribution data; and processing second characterization data by the trained model to generate second estimated distribution data. The second characterization data corresponds to a second semiconductor device different from the first semiconductor device.