3D IC Terminal Layout for Reliable Die-to-Die Interconnects
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Solution Overview
Problem
Three-dimensional integrated circuits face challenges with short circuits and disconnections of conductive terminals between vertically stacked dies, affecting power, performance, and area efficiency.
Innovation Solution
The solution involves arranging conductive terminals, such as edge bumps, to be spaced apart from the functional block boundaries by a minimum distance, preventing bump sweep and ensuring smooth signal transmission with minimal loss and distortion, while maintaining reliability and reusing the functional block design without additional verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conductive terminals are arranged close to the functional block boundary to maximize area utilization, then area efficiency is improved, but short circuits and disconnections may occur affecting reliability
Solution Approach 1:
The patent applies different spacing rules to different regions: edge conductive terminals are spaced at a first distance (greater than or equal to minimum distance) from the functional block boundary, while internal conductive terminals are spaced at a second distance (between first distance and twice the first distance) from each other. This localized quality differentiation maximizes area utilization while preventing short circuits and disconnections.
2Reliability
If conductive terminals are spaced further apart to prevent short circuits, then reliability is improved, but area utilization decreases
Solution Approach 1:
The patent changes the spacing parameter based on terminal position: a first distance (≥ minimum distance) for edge terminals from boundaries, and a second distance (between first distance and twice the first distance) for internal terminal-to-terminal spacing. This parameter differentiation achieves both reliability and area efficiency.
3Productivity
If more conductive terminals are added to increase integration capacity, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments conductive terminals into two categories: edge conductive terminals (at the periphery of the functional block) and internal conductive terminals (within the functional block). This segmentation enables systematic arrangement with different spacing rules, facilitating higher integration capacity while managing complexity through organized placement patterns.
Data Source
AI summary
Provided is a three-dimensional integrated circuit. The three-dimensional integrated circuit includes: a first die having a first surface and a second surface opposite each other; and a second die vertically stacked on the first surface of the first die. The first die includes: a functional block arranged on the first surface of the first die; and a plurality of conductive terminals arranged on the functional block and electrically connecting the first die to the second die. The plurality of conductive terminals include a plurality of edge conductive terminals arranged on an edge region of the functional block, and the plurality of edge conductive terminals are each spaced apart from a boundary of the functional block by a first distance that is greater than or equal to a minimum distance between the plurality of conductive terminals.