3D IC Through-Layer Vias for Yield and Reliability
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Solution Overview
Problem
The development of three-dimensional integrated circuits (3D ICs) faces challenges in yield and reliability due to the complexity of the systems, particularly in deep submicron process generations, and existing testing techniques are not adequately adapted for these complex structures.
Innovation Solution
A 3D IC system is designed with programmable layers of tiles and redundancy layers, where each tile comprises a microcontrol unit (MCU) communicating with adjacent MCUs, and through-layer vias of less than 200 nm diameter are used to connect the layers, enabling flexible configuration and testing through programmable connections and multiplexers, and allowing for the integration of logic circuits with direct-write-ebeam defined metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through Silicon Via technology is used to bond multiple layers of silicon to form 3D IC, then the integration density and functionality are improved, but the yield and reliability deteriorate due to system complexity
Solution Approach 1:
The patent segments the 3D IC system into multiple functional layers (logic layer, memory layer, I/O layer) that can be independently fabricated, tested, and repaired. Each layer operates as a modular unit with dedicated through-layer vias, allowing localized repairs without replacing the entire device, thus improving yield while maintaining high integration density.
Solution Approach 2:
The patent changes the physical parameters of through-layer vias by reducing their diameter to less than 200 nm, enabling higher density interconnections. This parameter change allows more connections per unit area, increasing integration density while the selective placement and sizing of vias optimizes reliability by reducing congestion and stress in critical paths.
2Device complexity
If deep submicron process generations are used to increase device complexity and functionality, then the computational power is improved, but the yield and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D integration to three-dimensional stacking, adding the vertical dimension to device architecture. This allows complex functionality to be distributed across multiple layers rather than confined to a single plane, enabling high device complexity while improving yield through modular fabrication and testing of individual layers before assembly.
3Ease of manufacture
If existing testing techniques are applied to 3D IC structures, then the manufacturing process is simplified, but the testing adequacy deteriorates
Solution Approach 1:
The patent implements preliminary testing of individual layers before they are bonded together in the 3D stacking process. This preliminary action allows defects to be detected and addressed in isolated layers rather than in the complete assembled device, improving testing adequacy while maintaining manufacturing simplicity through standardized test interfaces that work with both individual layers and assembled structures.
Data Source
AI summary
A method to construct a semiconductor device, the method including: forming a first layer including mono-crystallized semiconductor and first logic circuits; forming a second layer including a mono-crystallized semiconductor layer, the second layer overlying the first logic circuits; forming transistors on the second layer; forming connection paths from the second transistors to the first transistors, where the connection paths include a through layer via of less than 200 nm diameter; and connecting the first logic circuits to an external device using input/output (I/O) circuits, the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.