3D IC Via Structure for Front-to-Backside Die Interconnect
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating semiconductor devices with different process nodes and functionalities efficiently and cost-effectively, particularly in stacked semiconductor devices, where vertical electrical connections are difficult to achieve without increasing the form factor and production costs.
Innovation Solution
A unified via design is implemented, extending from the topmost conductive line of the interconnect structure to the backside of the specialty technology device, allowing for vertical electrical connections between front and backside redistribution structures, enabling integration of devices with varying process nodes and functionalities in three-dimensional integrated circuits (3DICs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar integration methods are used, then manufacturing simplicity is maintained, but integration density and bandwidth are limited
Solution Approach 1:
The patent transitions from planar (2D) integration to three-dimensional (3D) stacked integration, stacking multiple semiconductor dies vertically to achieve higher integration density. This dimensional change allows more components to be integrated within the same footprint area, directly resolving the contradiction between integration density and device structure complexity.
Solution Approach 2:
The patent implements a stacked die architecture where multiple semiconductor dies are nested vertically one on top of another, with each die containing functional circuits. This nesting approach maximizes the use of vertical space to increase integration density while maintaining manageable complexity through modular design.
2Volume of moving object
If vertical stacking is implemented to reduce form factor, then device size is reduced, but achieving vertical electrical connections becomes difficult and costly
Solution Approach 1:
The patent incorporates through-silicon vias (TSVs) and conductive interconnect structures during the semiconductor die fabrication process itself, before stacking. This preliminary formation of vertical connection pathways simplifies the overall manufacturing by integrating vertical connection creation into standard fabrication steps rather than adding complex post-stack processing.
Solution Approach 2:
The patent uses redistribution layers (RDLs) and conductive interconnect structures as intermediary elements between stacked dies. These intermediaries facilitate electrical connections between vertically stacked dies by providing conductive pathways that bridge different die interfaces, simplifying the manufacturing of vertical connections.
3Adaptability or versatility
If heterogeneous devices with different process nodes are integrated, then functionality and performance are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs a universal stacked die architecture with standardized TSV and redistribution layer structures that can accommodate semiconductor dies from different process nodes and functional types. This universal interface design allows heterogeneous integration (e.g., logic dies with memory dies, different process nodes) while maintaining relatively simple and consistent manufacturing processes across all stacked components.
Data Source
AI summary
A package includes a die. The die includes: a substrate; electrical components at a front side of the substrate; an interconnect structure at the front side of the substrate and electrically coupled to the electrical components, where an uppermost conductive line of the interconnect structure is an aluminum line; and a via extending from the uppermost conductive line to a backside of the substrate. The package further includes: a molding material around the die; a first redistribution structure (RDS) under the die and the molding material; a second RDS over the die and the molding material, where each of the first RDS and the second RDS comprises dielectric layers and conductive features in the dielectric layers, where the via of the die is electrically coupled to the first RDS and the second RDS; and a second die over and electrically coupled to the second RDS.