3D Imaging Sensor Structure with Stacked Logic and Pixel Wafers
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Solution Overview
Problem
Existing imaging sensors face issues such as process tuning impacting logic circuit area, low quantum efficiency, and full well capacity due to small pixel layout, and a larger image signal processor layout leading to low gross die count per unit area.
Innovation Solution
A 3D imaging sensor structure is developed, where two IC chips are stacked and mechanically bonded, with one chip dedicated to image sensors and the other to logic and driving circuits, allowing for independent tuning and optimization of both components, and electrical coupling through features like backside deep contacts or through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If logic circuit and pixel array are integrated on the same Si wafer, then device integration is achieved, but process tuning impacts logic circuit area and manufacturing precision deteriorates
Solution Approach 1:
The patent divides the imaging sensor into two separate wafers: one dedicated to pixel arrays and another to logic circuits and image signal processors. This segmentation allows independent fabrication and optimization of each component, eliminating the interference between process tuning for pixels and logic circuit area constraints while maintaining integration through wafer-level bonding.
2Area of stationary object
If pixel layout is made small to increase density, then area efficiency improves, but quantum efficiency and full well capacity deteriorate
Solution Approach 1:
The patent transitions from 2D planar integration to 3D stacked architecture, allowing pixels to be arranged in multiple layers. This enables larger effective pixel area and improved quantum efficiency while maintaining high density through vertical stacking, resolving the contradiction between small pixel layout and adequate quantum efficiency.
3Adaptability or versatility
If image signal processor layout is enlarged to improve functionality, then ISP performance improves, but gross die count per unit area deteriorates
Solution Approach 1:
The patent separates the image signal processor onto a dedicated wafer distinct from the pixel array wafer. This allows the ISP to be optimized for functionality without constraining the pixel density, while wafer-level bonding maintains compact integration. The segmentation enables independent scaling of ISP capabilities without compromising gross die count.
4Adaptability or versatility
If 3D stacked architecture is implemented with separate wafers for pixels and logic, then independent optimization is enabled, but device complexity increases
Solution Approach 1:
The patent introduces wafer-level bonding as an intermediary technique to connect the pixel array wafer and logic circuit wafer. This bonding interface serves as a mediator that enables independent optimization of each wafer while maintaining a relatively simple integrated structure, avoiding the complexity of fully 3D stacked approaches with multiple interconnect layers.
Data Source
AI summary
The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a second interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first interconnect structure and second interconnect structure are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.