3D Independent Double Gate Flash Memory for High Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-density three-dimensional memory devices face challenges in achieving reliable data storage due to field enhancement issues that lead to charge disturbance during read and program operations, limiting data density and increasing manufacturing costs.
Innovation Solution
A 3D memory device configuration with independent double gate, multiple-bit per cell operation is implemented, using hole-shaped etching to form vertical channel structures and isolation pillars, allowing for shared word lines and separate programming of each side of the memory cell, resulting in two charge storage sites per cell capable of storing 4 bits or more.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel diameter is reduced to increase memory density, then data density is improved, but field enhancement causes charge disturbance during read and program operations
Solution Approach 1:
The patent divides the single gate structure into two independent gates (first gate and second gate) positioned on opposite sides of the vertical channel. This segmentation allows independent control of each gate, enabling separate programming operations that reduce mutual interference and field enhancement effects, thereby maintaining charge storage reliability while achieving high density through the reduced channel diameter.
Solution Approach 2:
The patent applies different voltages and control strategies to each gate independently. The first gate and second gate can be programmed separately with optimized voltage pulses, allowing local optimization of the electric field distribution at each gate-channel interface. This local quality control minimizes field enhancement and charge disturbance while maintaining the benefits of the small channel diameter for high density.
2Quantity of substance
If multiple-bit per cell programming is implemented to increase density, then data density is improved, but fine control over threshold voltages becomes more critical and difficult
Solution Approach 1:
The independent double gate structure enables separate programming of the first and second gates, creating distinct charge trapping regions. This segmentation allows multiple threshold voltage states to be achieved through different combinations of gate programming, facilitating multiple-bit per cell operation with improved control over threshold voltage distribution and reduced interference between stored bits.
3Reliability
If a larger cross-section is used to reduce field enhancement, then charge disturbance is reduced, but memory device density is limited
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional independent double gate configuration where gates are positioned on opposite sides of the vertical channel. This dimensional change allows the channel diameter to remain small for high density while the distributed gate structure provides spatial separation that reduces field enhancement and charge disturbance, achieving both high density and high reliability simultaneously.
Data Source
AI summary
A memory device configurable for independent double gate cells, storing multiple bits per cell, includes multilayer stacks of conductive strips configured as word lines. Active pillars are disposed between pairs of first and second stacks, each active pillar comprising a vertical channel structure extending from an underlying bounded conductive layer, a charge storage layer and an insulating layer. The insulating layer in a frustum of an active pillar contacts a first arcuate edge of a first conductive strip in a layer of the first stack and a second arcuate edge of a second conductive strip in a same layer of the second stack. The conductive strips can comprise a metal. The active pillar can be generally elliptical with a major axis parallel with the first and second conductive strips.