3D Integrated Circuit Production via Segmented Interconnection
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Solution Overview
Problem
Current methods for producing three-dimensional integrated electronic circuits face challenges such as alignment issues during parallel integration, over-etching or under-etching problems, contamination of electrical interconnections, and thermal budget-related degradation, which limit the density of electronic components and the ability to insert local electrical interconnections and thermal/electrostatic screens.
Innovation Solution
A method where the production of the first portion of electrically conductive material precedes the second dielectric and semiconductor layers, followed by the production of electronic components, allowing for sequential connection and avoiding alignment issues, over-etching, and thermal contamination, while enabling the integration of local electrical interconnections and thermal/electrostatic screens between levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If parallel integration is used to increase integration density, then the number of electronic components per unit area increases, but alignment precision deteriorates due to limited bonding alignment performance
Solution Approach 1:
The patent segments the electrical interconnection formation into two independent stages: first forming conductive portions in the lower circuit layer, then forming separate contact holes through the upper circuit layer to connect to these conductive portions. This segmentation eliminates the need for high-precision alignment during bonding, as each layer can be processed independently with standard alignment tolerances.
Solution Approach 2:
The patent performs preliminary actions by forming the electrically conductive portions in the lower circuit layer before bonding the upper layer. This allows the upper layer to be bonded without requiring precise alignment to specific features, and the contact holes are subsequently formed to connect to the pre-formed conductive portions, thereby resolving the alignment precision issue while maintaining high integration density.
2Manufacturing precision
If sequential integration is used to avoid alignment issues, then manufacturing complexity increases due to multiple fabrication steps
Solution Approach 1:
The patent merges the advantages of both parallel and sequential integration by combining independent layer fabrication (parallel approach) with a simplified interconnection process. The conductive portions are formed as part of the lower layer fabrication, and contact holes are formed through the upper layer to connect to these portions, creating a unified process that achieves both alignment precision and manufacturing efficiency.
3Quantity of substance
If local electrical interconnections are implemented in dense areas, then integration density increases, but manufacturing precision requirements increase beyond current alignment capabilities
Solution Approach 1:
The patent segments the interconnection structure into conductive portions formed in the lower layer and contact holes formed through the upper layer. This segmentation allows local electrical interconnections to be implemented in dense areas without requiring high-precision alignment, as the conductive portions can be formed independently and the contact holes are subsequently connected to them using standard alignment tolerances.
Data Source
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AI summary
Method for making a three-dimensional integrated electronic circuit (100) comprising the steps of: - making a first conductive portion (124) on a first dielectric layer (112) covering a first semiconducting layer (108); - making a first electronic component (162, 164) in a second semiconducting layer (156) arranged on a second dielectric layer (118, 120, 126, 132, 134, 136, 142, 148, 160) covering the first conductive portion, and a second electronic component (170, 172) in the first semiconducting layer;- implementation of an electrical interconnection electrically linking the first and second electronic components together, of which a first part (182) passes through the first dielectric layer and electrically connects the second electronic component to the first conductive portion, and of which a second part (196) passes through at least a part of the second dielectric layer and electrically connects the first electronic component to the first conductive portion.;