3D Laminated Cell Array Structure for Semiconductor Memory Integration
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Solution Overview
Problem
Conventional semiconductor memory devices, particularly PRAMs with two-dimensional structures, have reached integration limits, necessitating a more efficient and compact three-dimensional structure to enhance data storage capacity and reduce power consumption.
Innovation Solution
A semiconductor memory device with a three-dimensional laminated cell array structure, comprising multiple layers of word lines and bit lines with memory cells at intersections, each including a variable resistance device in series with a diode, allowing for independent control of word lines and bit lines to optimize data storage and retrieval operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional cell array structure is used, then the device structure is simple and easy to manufacture, but the integration density is limited and leakage current increases
Solution Approach 1:
The patent transitions from a conventional two-dimensional cell array structure to a three-dimensional structure by stacking multiple cell array layers vertically. Each layer includes word lines, bit lines, and memory cells arranged in a grid, with subsequent layers positioned above previous layers. This vertical stacking enables higher integration density while maintaining the simplicity of individual layer fabrication, effectively resolving the contradiction between manufacturing ease and integration density.
2Device complexity
If a two-dimensional cell array structure is used, then the device structure is simple, but leakage current increases
Solution Approach 1:
By implementing a three-dimensional stacked architecture, the patent increases the distance between selected and non-selected memory cells in the vertical direction. This spatial separation reduces parasitic coupling and leakage current paths that exist in planar two-dimensional structures, thereby suppressing leakage current while keeping each individual layer relatively simple in structure.
3Quantity of substance
If more memory cells are integrated in a two-dimensional structure, then storage capacity increases, but leakage current and power consumption increase
Solution Approach 1:
The patent achieves high storage capacity by stacking multiple cell array layers vertically, each containing numerous memory cells. This vertical arrangement allows dense integration of memory cells without the proportional increase in leakage current that occurs in two-dimensional scaling, as the three-dimensional structure provides better isolation and reduces parasitic effects.
Solution Approach 2:
The patent divides the memory array into multiple independent cell array layers, each with its own set of word lines and bit lines. This segmentation allows selective activation of specific layers during read/write operations, enabling storage capacity scaling while maintaining low leakage current by only activating necessary layers and keeping others in a low-power state.
4Quantity of substance
If a three-dimensional cell array structure is implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The patent implements a three-dimensional structure by stacking multiple identical or similar cell array layers vertically, with each layer containing word lines, bit lines, and memory cells. While the overall device becomes more complex due to multiple layers, each individual layer maintains a relatively simple two-dimensional structure that is easy to manufacture, thus achieving high integration density with manageable per-layer complexity.
Solution Approach 2:
The patent combines multiple cell array layers into a single integrated three-dimensional structure, sharing common bit lines or word lines across layers where applicable. This merging approach increases integration density while managing device complexity by consolidating certain functions and reducing the total number of independent interconnects compared to having completely separate two-dimensional arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enables high integration and reduced leakage current, facilitating efficient data storage and retrieval while maintaining low power consumption, thereby overcoming the limitations of two-dimensional structures.
Implementation Method 1
The phase change material may include a material, such as a chalcogenide, in which a phase of the material is changed in response to a temperature change. Changing the phase of the material may also change the resistance of the material.
Implementation Method 2
A material such as GexSbyTez (hereinafter, referred to as 'GST') may be used as the phase change material
Data Source
AI summary
A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.