Digital Storage TRIZ Cases

A whole-domain-crossing-unit reset signal generator synchronizes counter timing with the data clock preparation section.

Low-temperature thermal depolarization bake detects imprint failures in ferroelectric capacitors without causing irreversible material damage.

Segmenting the write pulse reduces temperature rise and thermal crosstalk during multi-valued data storage in phase change memory.

An I/O module fits into a DIMM socket to provide serial data communication via PCIe or SATA interfaces.

Access circuit selects word-lines and determines refresh actions according to retention capability, reducing standby current consumption.

A shared current limiter allows multiple SRAM keepers to use smaller core transistors, reducing total circuit area while maintaining data retention reliability.

A sense amplifier architecture matches load currents using transistors and switches without feedback loops to reduce parasitic capacitance effects.

A content addressable memory uses two ferroelectric field effect transistors per bit cell to replace conventional sixteen-transistor structures.

Adjustable internal clock edges synchronize read data output to enable precise address access time measurement during semiconductor testing.

Memristive synapses adjust conductance through temporal pulse overlap to enable unsupervised learning in artificial neural networks.

Write-assist-keeper devices switch power supply connections to isolate SRAM cells from instantaneous voltage drops, enhancing read and write margins.

Segmenting power supplies into distinct voltage sources allows the sense amplifier to operate at lower voltages while maintaining read operation margins.

A resistive-switching device performs multiary addition operations through controlled resistance state changes.

Stacking multiple cell array layers vertically increases storage capacity while reducing leakage current through improved isolation between word and bit lines.

Array-transistor bias devices drop supply voltage to minimize power consumption while maintaining data retention reliability.

Segmented liner structures lower contact resistance between phase change materials and electrodes, improving device performance within thermal budgets.

A global reference circuit generates a control signal to stabilize resistance values across multiple memory sense amplifiers.

Multiplexing in a configurable storage block implements FIFO modules and shift registers, reducing logic resource usage and routing congestion.

Replacing digital blocks with a memristor reduces area and power while generating non-linear outputs.

A memory cell control method adjusts transistor gate and node voltages to set distinct impedance states for programming and resetting operations.

Replacing traditional transistors with thyristors in a content addressable memory cell reduces area intensity while maintaining reliable match detection.

Replica memory cells generate timing signals matching read/write cell behavior, resolving accuracy-area trade-offs under process variations.

A buried word line structure uses multiple gate dielectric layers with varying dielectric constants to increase on-current in dynamic random access memory.

Back-bias circuit dynamically adjusts node voltage to compensate for process-voltage-temperature variations and improve data retention.

Locating row hammer refresh circuitry outside the bank logic region allows shared components that mitigate data degradation while reducing die size.

Tracking circuits adjust virtual supply and ground voltages based on retention noise margin to prevent data loss during standby mode.

Memory controller uses dynamic throttling modes based on temperature readings to maximize system performance while preventing overheating.

A memory device samples command and data signals using four phase clock signals, eliminating synchronization time for faster data transfer.

A memory access control unit calculates burst access counts for address sets to optimize data retrieval speed.

Precharging sensing and first nodes to distinct voltage levels develops a resistance-based voltage, reducing read operation time while improving sensing margin.

A bit line regulator with a capacitor divider adjusts voltage levels based on resistive element states to enhance transistor strength.

Local plate line decoders control segmented plate lines to improve noise immunity and write speeds while maintaining data retention.

High capacitance power mode switches delay signal transmission through series switching devices, spreading precharge current over time to reduce peak currents.

Dynamic back bias voltage adjustment for memory cell transistors improves data storage reliability while reducing transistor stress during write operations.

Grouping MRAM cells with distinct reference values eliminates intermediate state overlap, reducing data errors and improving write reliability.

Angled bottom plugs in a spin-orbit torque layer enable field-free magnetic moment reversal, boosting write speed while simplifying device structure.

A read circuit precharges word lines to ground and bit lines to power before data detection.

An assist circuit dynamically adjusts target voltage levels to optimize memory cell access operations.

Control driver adjusts set current to recover resistance drift in phase-change memory cells, preventing material degradation and reducing energy consumption.

Dynamic bitline strapping reduces write resistance via passgates while minimizing capacitance to preserve read access time.

A magnetic memory device uses voltage to create a potential energy profile that controls domain wall position within a magnetic wire.

A semiconductor memory device adjusts auto-refresh operations using a temperature detector and refresh number setting unit.

Merging gate voltage generation into a single unit with a multiplexer reduces power consumption and area occupied in resistive memory devices.

Asymmetric data path positioning places the first pre-fetch column field closest to the main bus, reducing gate delays and improving high speed memory access.

A control circuit adjusts SRAM source line voltage to minimize leakage current during shutdown mode.

Oscillator and signal controller generate stable refresh period signals for semiconductor memory circuits.

Multi-phase control signals applied to SRAM word lines prevent logical state flipping under low voltage conditions, ensuring reliable data integrity.

A parallel bit test circuit compresses data and converts bus width to reduce output pin requirements.

Extending the trailing edge duration of applied pulses lowers conductance levels in phase-change memory, resolving precision limits during resetting operations.