Memory Device Multi-Phase Clock Sampling
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Solution Overview
Problem
Existing memory systems face challenges in synchronizing write clock signals with clock signals during data operations, requiring additional time and components for synchronization.
Innovation Solution
A memory system utilizing multiple phase clock signals, where a memory controller generates first, second, third, and fourth clock signals with the same frequency, allowing the memory device to sample command/address signals based on the first and third clock signals and data signals based on all four clock signals, eliminating the need for separate synchronization components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a write clock signal with higher frequency is used for high-speed data input/output, then data transfer speed is improved, but synchronization time with the clock signal increases
Solution Approach 1:
The clock signal is segmented into multiple phase signals (first clock signal, second clock signal, third clock signal, fourth clock signal) with different phases. This segmentation allows parallel sampling of data signals at different phases, eliminating the need for sequential synchronization and reducing the time required to handle high-speed data transfer.
Solution Approach 2:
The memory device performs periodic sampling of data signals using clock signals with different phases. By alternating between different phase signals for sampling, the system achieves continuous high-speed data transfer while maintaining synchronization, as each phase captures data at optimal timing intervals.
2Productivity
If multiple clock signals with different phases are used for sampling, then sampling efficiency is improved, but device complexity increases
Solution Approach 1:
The clock signal generation circuit is designed to generate multiple phase signals (first, second, third, and fourth clock signals) from a single reference clock signal. This multi-functional approach allows the same circuit to serve multiple sampling purposes simultaneously, improving sampling efficiency without proportionally increasing overall device complexity.
3Reliability
If separate synchronization components are added to synchronize write clock and clock signals, then synchronization accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The synchronization function is merged with the clock signal generation and data sampling process. Instead of using separate synchronization components, the system achieves synchronization by using multiple phase clock signals that are inherently aligned through their phase relationships, thereby reducing device complexity and power consumption while maintaining synchronization accuracy.
Data Source
AI summary
A memory device includes: a memory bank including a plurality of memory cells; and a memory interface circuit configured to store data in the plurality of memory cells based on a command/address signal and a data signal, wherein the memory interface circuit includes: first, second, third and fourth pads configured to receive first, second, third and fourth clock signals, respectively; a first buffer circuit configured to sample the command/address signal in response to an activation time of the first and third clock signals which have opposite phases from each other; and a second buffer circuit configured to sample the data signal in response to the activation time of the first clock signal, an activation time of the second clock signal, the activation time of the third clock signal and an activation time of the fourth clock signal.