Row Hammer Refresh Circuit Layout Sharing Bank Logic Region
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Solution Overview
Problem
In semiconductor memory devices, the increased density of memory cells leads to data degradation in nearby cells due to 'row hammer' effects, where repeated access to a particular row causes decay in neighboring rows, necessitating effective identification and refresh of affected memory cells, but existing circuitry for this purpose requires significant layout area, increasing die size.
Innovation Solution
Locating at least some components of the row hammer refresh circuitry outside the bank logic region, such as in a central command region, allows for sharing of circuits and reduces congestion, thereby minimizing the increase in die size without detrimental effects on performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuitry for identifying and refreshing row hammer affected memory cells is implemented, then data degradation from row hammer effects is mitigated, but die size increases due to significant layout area requirements
Solution Approach 1:
The patent combines the row hammer refresh circuitry with existing bank logic region infrastructure by sharing word line buffers and control logic. The aggressor detector circuit and refresh control circuit are integrated into the bank logic region, utilizing existing circuit elements to reduce the additional area required while maintaining the ability to identify and refresh affected memory cells.
Solution Approach 2:
The bank logic region circuits are designed to serve multiple functions: normal memory bank control and row hammer detection/refresh operations. The word line buffers and control logic can operate in both standard memory access modes and row hammer mitigation modes, eliminating the need for dedicated separate circuitry and reducing overall die size.
2Speed
If row hammer refresh circuitry is placed within the bank logic region, then performance is maintained, but congestion increases in the bank logic region
Solution Approach 1:
The patent segments the row hammer refresh functionality into distinct modular components: aggressor detector circuit, refresh control circuit, and word line buffers. These segmented modules are distributed within the bank logic region, allowing for organized signal routing and reduced interference between circuits, thereby managing congestion while maintaining performance.
3Quantity of substance
If dense memory cell layout is implemented to increase storage density, then storage capacity increases, but row hammer effects cause increased data degradation in nearby cells
Solution Approach 1:
The aggressor detector circuit continuously monitors and identifies rows that are being repeatedly accessed (aggressor rows) before significant damage occurs to neighboring cells. The refresh control circuit then proactively triggers refresh operations on adjacent victim rows, preventing data degradation rather than merely responding to it after damage occurs. This preliminary action approach allows dense packing while mitigating the harmful effects through early detection and prevention.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses, systems, and methods for providing refresh logic, such as row hammer refresh circuitry, in a location on a memory die apart from a bank logic region of the memory die. In some examples, at least some of the components of the row hammer refresh circuitry may be shared between banks of the memory.