FeFET-Based Content Addressable Memory Area Reduction
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Solution Overview
Problem
Conventional ternary content addressable memories (TCAMs) based on metal-oxide semiconductor field effect transistors are large in size and consume high power due to the need for 16 transistors per bit cell, leading to increased area and power consumption.
Innovation Solution
A content addressable memory (CAM) using ferro-electric field effect transistors (FeFETs) with each bit cell comprising only two FeFETs, where the source of one FeFET is connected to the drain of the other and grounded, reducing the size and power consumption by optimizing transistor connections and voltage settings for match line operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOS-based TCAM with 16 Ts per bit cell is used, then data storage and comparison function is achieved, but area consumption is large
Solution Approach 1:
The patent changes the transistor type from conventional MOS to FeFET (ferroelectric field-effect transistor), utilizing the ferroelectric effect to achieve non-volatile storage with significantly reduced transistor count per bit cell (from 16 to 2), thereby reducing area consumption while maintaining storage and comparison functions
Solution Approach 2:
The patent extracts and removes redundant transistors from the conventional 16-T structure, keeping only the essential 2 FeFETs needed for storage and comparison operations, thus achieving area reduction without sacrificing functional reliability
2Reliability
If conventional MOS-based TCAM with 16 Ts per bit cell is used, then data storage and comparison function is achieved, but power consumption is high
Solution Approach 1:
The patent changes the transistor type to FeFET which offers non-volatile storage capability, eliminating the need for continuous refresh operations required by volatile MOS-based TCAM, thereby significantly reducing power consumption while maintaining data storage and comparison functions
Solution Approach 2:
The patent removes the refresh circuitry and associated transistors needed in conventional MOS-TCAM, keeping only the essential 2 FeFETs per bit cell, thus eliminating unnecessary power consumption from refresh operations
3Area of stationary object
If FeFET-based 2T bit cell structure is used, then area and power consumption are reduced, but matching precision must be maintained
Solution Approach 1:
The patent utilizes the ferroelectric effect in FeFETs to achieve stable binary states (0 and 1) with distinct voltage thresholds, ensuring precise matching operations despite the reduced 2T structure, thereby maintaining measurement precision while reducing area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CAM design significantly reduces area and power consumption while maintaining efficient data processing and matching capabilities, enabling smaller and more energy-efficient network devices.
Implementation Method 1
each bit cell includes a first ferro-electric field effect transistor (ferro-electric field effect transistor, FeFET) and a second FeFET
Data Source
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AI summary
This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row. The CAM may be applied to a network device such as a router.