Thyristor-Based CAM Cell Reduces Transistor Count

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Solution Overview

Problem

Content addressable memories (CAMs) are typically area intensive due to the requirement of multiple transistors per cell, making them inefficient in terms of space usage.

Innovation Solution

The use of thyristor-based memory technology reduces the number of transistors required per CAM cell by employing two thyristors per cell, optimizing the storage and match operations through specific voltage levels and conductivity states for data, don't care match, and don't care mismatch bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional CAM cells use multiple transistors per cell, then match and mismatch detection functionality is achieved, but area intensity increases

Engineering Contradiction:
Improvematch and mismatch detection functionalityVSAvoidarea intensity
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent replaces the traditional transistor-based CAM cell with a thyristor-based implementation. Thyristors are semiconductor devices that can maintain their state without continuous power, enabling match and mismatch detection with fewer components. This substitution of the underlying semiconductor device reduces the transistor count while preserving the essential CAM functionality.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent utilizes the unique electrical characteristics of thyristors, specifically their ability to exist in stable conductive and non-conductive states, to encode data and perform match/mismatch detection. By changing the operational parameters and state management approach from traditional transistor switching to thyristor latching behavior, the design achieves reduced area intensity while maintaining detection reliability.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If thyristor-based memory technology is used, then number of transistors per cell is reduced, but device complexity in terms of voltage control and conductivity states increases

Engineering Contradiction:
Improvenumber of transistors per cellVSAvoidvoltage control and conductivity states
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The patent designs the thyristor-based CAM cell to perform multiple functions through a unified structure. The same thyristor configuration used for data storage also enables match detection, mismatch detection, and state maintenance. This multi-functionality approach reduces the need for separate control mechanisms for each operation, thereby managing the complexity of voltage control and conductivity states more effectively.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Thyristors possess the inherent ability to maintain their conductive or non-conductive state without continuous external control, providing self-latching behavior. This self-service characteristic reduces the need for complex continuous voltage control circuits, simplifying the overall device operation while maintaining reliable state representation for data storage and detection purposes.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7724567B2Memory device and method of refreshing
Publication Date: 2010.05.25 ADVANCED MICRO DEVICES INC
  • US7724567B2 patent drawing
  • US7724567B2 patent drawing
  • US7724567B2 patent drawing

AI summary

A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.