Semiconductor Device Clock Edge Adjustment for Wafer-Level tAA Testing
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Solution Overview
Problem
Semiconductor devices face challenges in measuring address access time (tAA) effectively due to limited data input/output paths and the need for improved data transfer speeds, which are hindered by the difficulty in detecting address access time during wafer-level testing.
Innovation Solution
A semiconductor system and test method that include a semiconductor device capable of outputting read data synchronized with a system clock, with adjustable clock edges to facilitate accurate measurement of address access time, utilizing a 'TCL05' mode that adjusts the clock edge shifting time to enhance data output and detection of valid output data windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data input/output speed is increased to meet higher operation speeds, then productivity is improved, but measurement precision of address access time deteriorates due to limited detection capability at wafer level
Solution Approach 1:
The patent introduces an intermediary clock adjustment mechanism that mediates between the fast data transfer requirements and the precise measurement needs. By inserting a controllable clock edge shifting unit in the test path, the system can slow down or adjust the effective measurement clock edges without affecting the actual high-speed data operation, enabling precise tAA measurement while maintaining high productivity
Solution Approach 2:
The patent implements dynamic clock edge adjustment capability where the clock phase and timing can be dynamically modified during testing. The clock adjustment unit can shift clock edges based on test requirements, allowing the measurement system to adapt its timing dynamically to capture address access time accurately even when data transfer operates at high speeds
2Productivity
If address access time measurement is performed at wafer level with high speed, then productivity is improved, but measurement precision deteriorates due to limited detection capability
Solution Approach 1:
The clock adjustment unit serves as an intermediary between the wafer-level test equipment and the semiconductor device under test. It provides a controllable timing reference that can be independently adjusted from the data transfer clock, enabling precise measurement of address access time without compromising the high-speed wafer-level testing process
Solution Approach 2:
The patent applies preliminary action by pre-adjusting the clock edges to optimal positions before actual measurement begins. The clock adjustment unit is configured in advance with appropriate timing offsets and phase shifts, so that when measurement starts, the clock edges are already positioned to capture the address access time window accurately, enabling both high throughput and precision
Data Source
AI summary
A semiconductor device includes a memory region suitable for providing a plurality of read data in parallel at every read operation cycle, an output path suitable for outputting the plurality of read data at a set time in response to an internal clock and one or more internal control signals at the every read operation cycle, and an output path control unit suitable for generating the internal control signal in response to a read command and generating the internal clock in response to a system clock, wherein a shifting time of a first edge of the internal clock is adjusted by a set level at the every read operation cycle during a test mode.