Configurable Storage Block with FIFO and Shift Register Modes
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Solution Overview
Problem
Conventional configurable storage blocks in integrated circuits are often underutilized, as they are typically designed for pure memory use, leaving unused resources and requiring additional logic and routing for implementing design constructs like shift registers and FIFO modules, which can lead to resource wastage and routing congestion.
Innovation Solution
A configurable storage block with control and arithmetic circuitry that allows operation in multiple modes, including RAM, shift register, and simple FIFO modes, using write and read address generation circuits and multiplexing to efficiently implement these constructs without the need for specific logic and routing resources, thereby reducing resource usage and congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If configurable storage blocks are designed for pure memory use only, then memory functionality is optimized, but additional logic and routing resources are required to implement design constructs like shift registers and FIFO modules
Solution Approach 1:
The configurable storage block is enhanced with control and arithmetic circuitry that enables it to perform multiple functions beyond basic memory operations. The block can be configured to operate as a memory array, shift register, or FIFO module through programmable control logic that generates read and write addresses based on operational mode, eliminating the need for separate dedicated hardware for each function.
2Device complexity
If configurable storage blocks are designed for pure memory use only, then memory operations are simplified, but routing congestion increases due to additional logic and routing resources
Solution Approach 1:
The invention merges the functionality of separate memory arrays, shift registers, and FIFO modules into a single unified configurable storage block. By integrating control and arithmetic circuitry that can dynamically generate addresses and manage data flow in different modes, the design eliminates the need for multiple independent hardware blocks and their associated routing, thereby reducing routing congestion.
3Productivity
If simple registers continuously output data without pause, then data flow is maximized, but errors occur when downstream circuitry is not ready to receive output data
Solution Approach 1:
The configurable storage block incorporates control circuitry that can monitor the state of downstream circuitry and adjust data output accordingly. In FIFO mode, the block can pause data output when the downstream buffer is full, using feedback signals to control the enablement of data output, thereby preventing data loss while maintaining high data flow rates when downstream circuitry is ready.
Data Source
AI summary
An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.