SRAM Source Line Voltage Control for Leakage Reduction
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Solution Overview
Problem
As transistor sizes decrease, SRAM cells experience high leakage currents in the off state, leading to increased static power consumption and incorrect data reads due to the accumulation of leakage current affecting bitline differentials.
Innovation Solution
A source-biasing scheme is implemented in SRAM cells, where a control circuit selectively connects the source line to different voltage levels, allowing it to float to a level equal to the first voltage in shutdown mode, reducing leakage by minimizing the voltage gradient across bitcells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor sizes are decreased to increase memory density, then more memory cells can be packed into smaller area, but leakage current in the off state increases significantly
Solution Approach 1:
The patent changes the voltage parameter of the source line dynamically. In shutdown mode, the source line is disconnected from the second voltage rail and allowed to float to a voltage level substantially equal to the first voltage, thereby reducing the voltage gradient across the bitcells and minimizing leakage current. This parameter change enables the system to maintain small transistor sizes while controlling the harmful leakage effect.
2Power
If high leakage current occurs in SRAM cells, then static power consumption increases, but this also causes incorrect data reads due to accumulated leakage current affecting bitline differentials
Solution Approach 1:
The patent introduces a dynamic control mechanism for the source line voltage. The control circuit selectively connects the source line to different voltage levels based on operational mode: connected to the second voltage during normal operation for proper data access, and disconnected (floating) during shutdown mode to minimize leakage. This dynamic adjustment resolves the contradiction between power consumption and data accuracy by adapting the voltage configuration to the operational requirements.
Data Source
AI summary
In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and includes a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed, a sleep mode is which data is retained but leakage is reduced and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage.