Memory Access Control Unit Burst Random Switching Logic
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Solution Overview
Problem
Existing memory access control methods are unable to efficiently switch between burst and random access for address sets with multiple target addresses, leading to suboptimal access times and reduced efficiency.
Innovation Solution
A semiconductor device that calculates the number of burst accesses and access times for address sets, determining whether adjacent addresses can be accessed together, and selectively chooses between burst and random access methods to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If burst access is used for address sets with multiple target addresses, then access efficiency is improved, but it becomes impossible to accurately estimate access time when burst access must be performed multiple times
Solution Approach 1:
The patent segments the address set into multiple groups that can be accessed by individual burst access operations. By dividing the total address set into sub-sets that fit within burst access capabilities, the system can accurately calculate access time for each segment and sum them, rather than attempting to estimate time for a single large burst access that may need to be split.
Solution Approach 2:
The patent performs preliminary calculation of the number of burst access operations needed before executing the access sequence. By pre-calculating how many burst accesses are required based on the total number of target addresses and burst access capacity, the system can accurately estimate total access time by multiplying the number of operations by the time per operation, resolving the estimation accuracy problem.
2Adaptability or versatility
If random access is used for each address, then access flexibility is maintained, but access latency increases due to repeated address designation
Solution Approach 1:
The patent merges multiple address accesses into a single burst access operation when the addresses form a contiguous sequence. By combining adjacent target addresses into one burst access command rather than issuing separate random access commands for each address, the system reduces the number of address designations and eliminates repeated latency periods, while still maintaining the ability to switch to random access when addresses are non-contiguous.
3Productivity
If burst access is used for large address sets, then fewer address designations are needed, but it becomes impossible to determine whether single or multiple burst accesses should be performed
Solution Approach 1:
The patent changes the parameter used for access control decision from complex pattern recognition to a simple numerical comparison. By using the relationship between the total number of target addresses and the burst access capacity (number of addresses per burst), the system determines the number of burst operations needed through straightforward division or comparison, avoiding complex control logic while maintaining high access efficiency.
Data Source
AI summary
A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a determination, for each of N addresses a1 to an (N is a natural number no less than two) included in the address set (A), whether or not the address and another address adjacent to that address in an accessing order can be accessed by the same burst access, and calculates an access time that will be taken for accessing the address set by the burst access.