Memory Cell Impedance Control via Dynamic Voltage Adjustment

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Solution Overview

Problem

Resistance type memory cells experience efficiency degradation over time, leading to errors in reading and writing due to impedance differentiation issues between low and high states.

Innovation Solution

A control method for memory cells comprising a transistor and resistor, where programming involves providing specific voltages to nodes and the gate, with impedance state changes to differentiate successful programming and resetting, using varying voltages to adjust impedance states effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If resistance type memory is used for long period operation, then memory capacity and operational duration are improved, but reading and writing errors increase due to impedance differentiation degradation

Engineering Contradiction:
Improveoperational durationVSAvoidreading and writing accuracy
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting voltage levels applied to the memory cell during read operations. As the memory cell undergoes programming and resetting cycles, its impedance characteristics drift over time. The system compensates for this degradation by modifying the read voltage parameters to maintain adequate signal differentiation between programmed and reset states, thereby preserving reading and writing accuracy throughout the memory's operational lifetime.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple voltage levels are applied to program and reset memory cells, then programming precision and reliability are improved, but device complexity and control circuit requirements increase

Engineering Contradiction:
Improveprogramming accuracyVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements multi-functionality by designing control circuits that can operate with multiple voltage levels while maintaining compatibility with standard memory cell structures. The same control circuitry that applies programming voltages also performs resetting and reading operations, eliminating the need for entirely separate circuit systems. This universal approach allows precise control of impedance states through varied voltage application without proportionally increasing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method ensures accurate programming and resetting of memory cells by maintaining or adjusting voltages to achieve desired impedance states, thereby reducing errors and maintaining efficiency over time.

Implementation Method 1

The impedance of a resistance type memory is easily differentiated between a low state and a high state

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS8817521B2Control method for memory cell
Publication Date: 2014.08.26 IND TECH RES INST
  • US8817521B2 patent drawing
  • US8817521B2 patent drawing
  • US8817521B2 patent drawing

AI summary

A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.