Asymmetric Data Path Positioning for High Speed DRAM Access
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Solution Overview
Problem
In high-density DRAM designs, the physical placement of column fields within memory banks leads to varying access times, with the farthest column field being the slowest, due to lack of preference in pre-fetch address placement, resulting in inefficient data access.
Innovation Solution
The asymmetric data path position and delays technique positions the first pre-fetch data column address field closest to the main data bus, with subsequent fields positioned farther away, and uses segmented column address buses to introduce delays, optimizing the data path for faster access by eliminating unnecessary clock signals and reducing gate delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If column fields are positioned symmetrically without preference in memory banks, then manufacturing simplicity is maintained, but access time increases due to farthest column field being slowest
Solution Approach 1:
The patent applies asymmetry by positioning column fields at different distances from the main data bus based on their access frequency. Specifically, column fields associated with earlier pre-fetch addresses are placed closer to the main data bus, while later column fields are positioned farther away. This asymmetric layout optimizes the critical path for most frequently accessed data, reducing overall access time despite increased layout complexity.
Solution Approach 2:
The patent implements local quality by creating different data path characteristics for different column fields. Each column field group has a customized data path length and complexity matched to its specific access timing requirements. This allows optimized performance for time-critical column fields while accepting longer paths for less time-sensitive fields, achieving overall system optimization.
2Speed
If data path is optimized for fastest access, then access speed improves, but data path complexity and pipeline complexity increase
Solution Approach 1:
The patent segments the data path into multiple independent paths corresponding to different column field groups. Each segment has its own optimized pipeline stages and clocking, allowing parallel processing of data from different column fields. This segmentation enables fast access for critical data while managing overall complexity through modular design.
Solution Approach 2:
The patent employs dynamic clocking and pipeline control where different column field groups can be activated at different times based on access patterns. The pipeline stages are dynamically enabled or disabled depending on which column fields are being accessed, optimizing performance for active paths while reducing unnecessary complexity in inactive paths.
Data Source
AI summary
An asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices which is asymmetric in terms of the delay from the array to the I/O buffers based on the position relative within a known starting address of a pre-fetch field. In accordance with the technique of the present invention, the delay is not only asymmetric in terms of its physical length, but also in the number of pipeline stages and the clocks that control them and can also be asymmetric in terms of the column address required to access each section of the array and its designated pre-fetch field.