Memory Precharge Circuitry Peak Current Reduction
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Solution Overview
Problem
Semiconductor memory storage devices face challenges in reducing power consumption and peak currents, particularly when transitioning from low power mode to operational mode, as simultaneous precharging of bitlines can lead to high peak currents that may damage the silicon and constrain design requirements.
Innovation Solution
The use of a high capacitance power mode switch, configured to provide a delay in powering up output lines, allows for controlled precharging by transmitting the power mode signal in series through switching devices, reducing peak currents and minimizing the impact of operating conditions, thereby spreading the precharge current requirements over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all bitlines are precharged simultaneously when returning from low power mode, then the bitlines reach full voltage quickly, but very high peak currents are generated that can collapse the power supply rail and damage the silicon
Solution Approach 1:
The patent divides the bitlines into multiple groups, each controlled by a separate precharge device. These precharge devices are activated at different times through a segmented control approach, where the control signal is delayed progressively for each subsequent group. This segmentation allows the total precharge current to be distributed across multiple time intervals rather than occurring simultaneously, thereby reducing the peak current while maintaining complete precharge of all bitlines.
2Object-generated harmful factors
If active devices such as inverter chains are used to add delay to control signals for reducing peak currents, then peak currents are reduced, but the delay varies with operating conditions and requires higher average delay to accommodate process corners
Solution Approach 1:
The patent introduces a preliminary delay mechanism that is built into the control signal path itself, rather than relying on active delay devices during operation. The control signal is deliberately delayed before being distributed to the precharge devices, and this delay is established as a fixed characteristic of the control logic. This preliminary action ensures that even at fastest process corners, the sequential activation of precharge devices is maintained, providing consistent peak current reduction without requiring excessive average delay.
3Power
If the precharge current is significantly higher than other currents during normal operation, then the memory design must account for peak current requirements, but this constrains the overall design flexibility
Solution Approach 1:
The patent implements a dynamic control mechanism where the precharge devices are activated in a sequential manner rather than simultaneously. The control signal is dynamically timed to activate each precharge device in sequence, allowing the system to adapt the precharge current profile to match the capabilities of the power supply. This dynamic approach transforms the static, simultaneous precharge into a controlled, time-distributed process, reducing peak current demands and thereby relaxing design constraints on power supply capacity and current handling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces peak currents without compromising memory performance, as only the switching from inactive to operational state is delayed, and not the data output switching, thus allowing for more efficient power management and reduced peak current demands.
Implementation Method 1
said power mode switch is configured to have a higher capacitance than said data output switch
Data Source
AI summary
A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal. The plurality of switching devices each comprising at least two switches, the at least two switches comprising a data output switch controlled by the data output request signal and a power switch controlled by the power mode signal, the plurality of switching devices connecting the output lines to the predetermined voltage in response to both the power mode signal indicating an operational mode and the data output request signal indicating data is to be output; wherein the power mode switch is configured to have a higher capacitance than the data output switch.