Diode-Connected Transistor Back-Bias for SRAM PVT Compensation
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Solution Overview
Problem
Conventional SRAM circuits face challenges in adapting to process-voltage-temperature (PVT) variations due to a fixed voltage level on nodes between the memory array and diode-connected PMOS transistors, which limits their ability to compensate for changes in voltage drops across these transistors.
Innovation Solution
Incorporating a back-bias circuit that adjusts the voltage applied to the bulk of the diode-connected PMOS transistor, allowing for a reverse bias during data retention mode, thereby changing the voltage drop across the transistor and adjusting the voltage level on the node between the memory array and the diode-connected transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed voltage level is used on the node between the memory array and diode-connected PMOS transistor, then the circuit structure is simple, but the ability to compensate for PVT variations is limited
Solution Approach 1:
The patent applies the dynamics principle by introducing a back-bias circuit that dynamically adjusts the voltage level on the node between the memory array and diode-connected PMOS transistor. Instead of using a fixed voltage, the circuit can now adapt the voltage level in response to PVT variations, thereby improving the ability to compensate for process, voltage, and temperature changes while maintaining reasonable circuit structure.
2Reliability
If the voltage drop across the diode-connected PMOS transistor is fixed, then the circuit is stable, but data retention performance cannot be optimized under varying conditions
Solution Approach 1:
The patent applies the parameter changes principle by modifying the voltage drop across the diode-connected PMOS transistor through the back-bias circuit. The circuit changes the voltage parameter dynamically based on PVT conditions, allowing optimization of data retention performance under varying process, voltage, and temperature conditions while maintaining stability through controlled adjustment rather than fixed parameters.
3Reliability
If a back-bias circuit is added to adjust the bulk voltage of the diode-connected PMOS transistor, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent applies the intermediary principle by introducing a back-bias circuit as an intermediate component between the power supply and the diode-connected PMOS transistor. This intermediary circuit adjusts the bulk voltage of the transistor to optimize data retention without requiring fundamental redesign of the entire SRAM cell structure, thereby improving reliability with minimal increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables dynamic adjustment of the voltage level on the node, allowing for improved data retention and reduced current consumption, effectively addressing the limitations of fixed voltage levels in SRAM circuits.
Implementation Method 1
a back-bias circuit that adjusts the voltage applied to the bulk of the diode-connected PMOS transistor, allowing for a reverse bias during data retention mode
Data Source
AI summary
A memory circuit including at least one memory array and at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage. The memory circuit further includes at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line and a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.