Multi-Pulse SRAM Control Signal for Low Voltage Read Stability

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Solution Overview

Problem

Static random access memory (SRAM) cells experience degradation in static noise margin (SNM) at low or ultra-low supply voltages, leading to unstable logical states during read cycles, causing reading operations to fail.

Innovation Solution

A multi-pulse control signal is applied to the word line of the SRAM cell, periodically switching between high and low voltage levels to manage discharging currents and prevent logical state flipping, thereby maintaining stable logical states during read cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If operating voltage is reduced to achieve lower power consumption, then energy efficiency is improved, but static noise margin degrades leading to unstable logical states

Engineering Contradiction:

Improvepower consumptionVSAvoidstatic noise margin

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies periodic clocking signals to the SRAM cell during read operations, using multi-phase control signals to periodically restore logical states. This periodic action counteracts the destabilizing effect of low voltage by rhythmically reinforcing the stored data states, thereby maintaining reliability while operating at reduced power consumption levels

Inventive Principle:

Principle #19Periodic action

2Device complexity

If single-pulse control signal is used to simplify control circuitry, then device complexity is reduced, but logical state stability cannot be maintained during read cycles

Engineering Contradiction:

Improvecontrol circuitryVSAvoidlogical state stability

Core Design Contradiction:

Device complexityVSStability of the object's composition

Solution Approach 1:

The control signal is segmented into multiple phases (first phase signal, second phase signal, third phase signal) that are applied at different times during the read cycle. This segmentation allows each phase to perform a specific function in maintaining logical state stability, achieving reliable operation without requiring overly complex control circuitry

Inventive Principle:

Principle #1Segmentation

3Reliability

If read cycle duration is extended to ensure complete read operation, then reading reliability is improved, but susceptibility to logical state flipping increases

Engineering Contradiction:

Improvereading operationVSAvoidread cycle duration

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

By applying periodic clocking signals throughout the extended read cycle, the patent maintains logical state stability over the longer duration. The multi-phase control signals are synchronized with the read operation timeline, providing state restoration at critical moments without requiring the entire read cycle to be continuously active, thus managing the trade-off between duration and reliability

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS10157664B2Memory controlling device by using multi-phase control signal and method thereof

Publication Date: 2018.12.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory controlling device includes: a control circuit arranged to generate a multi-pulse control signal with a first duration; and a memory cell coupled to a pair of bit lines and a word line, wherein the multi-pulse control signal is coupled to the word line, and the memory cell is arranged to output an output signal on the pair of bit lines during the first duration.