SRAM Assist Circuit Optimizes Voltage for Low Power Stability

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Static random access memory (SRAM) devices face instability and data loss at low supply voltages due to reduced static noise margin and process variations, leading to increased access failure probabilities, which existing access assist techniques often address inadequately, resulting in unnecessary power consumption.

Innovation Solution

A method and memory device with an assist circuit that determines a target assist voltage level by setting supply voltages to different levels, calculating a reference probability value, and applying an assist voltage to optimize assist strength, thereby reducing access failure probabilities without overestimating voltage decreases, thus improving power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If supply voltage is reduced to lower dynamic power dissipation, then power consumption is reduced, but SRAM cell stability deteriorates due to reduced static noise margin

Engineering Contradiction:

Improvedynamic power dissipationVSAvoidSRAM cell stability

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The assist circuit pre-charges the bit line to a voltage higher than the supply voltage (e.g., VDD + ΔV) before the read operation. This preliminary voltage boosting ensures that even when supply voltage is reduced for power savings, the bit line has sufficient voltage headroom to maintain proper read operation and overcome process variations, thus preserving SRAM stability at low power conditions.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If existing access assist techniques are applied to maintain SRAM stability, then access failure probability is reduced, but power consumption increases due to overestimating voltage decreases

Engineering Contradiction:

Improveaccess failure probabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The system includes a measurement circuit that actually measures the voltage decrease on the bit line during read operations, and a control circuit that adjusts the assist circuit's voltage boosting amount based on this measured feedback. This closed-loop feedback mechanism prevents overestimation of voltage decreases, ensuring that assist voltage is applied only when necessary and at the precise amount needed, thereby maintaining low access failure probability while minimizing unnecessary power consumption.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The assist circuit dynamically adjusts its assist voltage parameter (the voltage boosting amount ΔV) based on measured operating conditions. Rather than applying a fixed over-cautious assist voltage that wastes power, the system changes the assist parameter adaptively according to actual bit line voltage decreases, process conditions, and supply voltage levels, optimizing the trade-off between reliability and power consumption.

Inventive Principle:

Principle #35Parameter changes

3Loss of energy

If supply voltage is reduced, then dynamic power dissipation is reduced, but static noise margin deteriorates making the SRAM cell unstable

Engineering Contradiction:

Improvedynamic power dissipationVSAvoidstatic noise margin

Core Design Contradiction:

Loss of energyVSStability of the object's composition

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10692567B2Method for assisting memory cell in access operation and operating memory cell, and memory device having assist circuit with predefined assist strength

Publication Date: 2020.06.23 M31 TECH

AI summary

A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.