Parallel Bit Test Circuit for Semiconductor Memory
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Solution Overview
Problem
In highly integrated semiconductor memory devices, the increase in memory capacity and input/output lines leads to a significant increase in test time due to the reduction in the number of chips that can be simultaneously tested, particularly when parity bits for error correction are added, resulting in longer test times and increased costs.
Innovation Solution
A parallel bit test circuit and method that includes a plurality of data compressors, a delay unit, and a bus width converter, which compress data, generate delayed clock signals, and convert the data width to reduce the number of output pins required, allowing for more efficient testing by controlling the burst length and serially outputting data to minimize test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory capacity and input/output lines are increased, then manufacturing precision and reliability are improved, but test time increases significantly
Solution Approach 1:
The patent segments the test data into multiple groups and processes them in parallel through multiple data compressors simultaneously. Instead of testing all memory cells sequentially, the test circuit divides the large memory array into segments that can be tested concurrently, reducing overall test time while maintaining comprehensive coverage of increased memory capacity.
Solution Approach 2:
The patent transitions from sequential single-bit testing to parallel multi-bit testing by adding temporal dimension through burst mode operations. Multiple data bits are tested simultaneously across multiple data lines and compressed in parallel, effectively adding a time dimension to the testing process that reduces total test duration despite increased memory capacity.
2Reliability
If parity bits for error correction are added, then reliability is improved, but test time increases
Solution Approach 1:
The patent merges the testing of data bits and parity bits into a single unified parallel testing operation. Instead of separately testing data cells and then parity cells, the test circuit simultaneously tests both through the same data compressors and logic circuits, reducing overhead time while maintaining the reliability benefits of error correction coding.
Solution Approach 2:
The patent maintains continuous useful action by ensuring that parity bit testing occurs concurrently with data bit testing rather than sequentially. The test circuit continuously processes both data and parity information through parallel pathways, eliminating idle time and keeping all test resources actively engaged throughout the testing process.
3Manufacturing precision
If the number of data lines increases, then manufacturing precision is improved, but the number of output pins required increases
Solution Approach 1:
The patent extracts redundant information from multiple data lines through data compression. Multiple data lines carrying similar or redundant test data are fed into compression circuits that extract the essential pass/fail information, reducing the number of output pins needed while maintaining the ability to monitor all data lines for manufacturing defects.
Solution Approach 2:
The patent introduces data compressors as intermediary components between the numerous data lines and the limited output pins. These compressors act as mediators that aggregate information from multiple sources and present condensed results to the output, reducing the direct connection requirement between data lines and output pins while preserving test functionality.
4Productivity
If parallel bit test is performed, then productivity is improved, but the number of output pins required increases
Solution Approach 1:
The patent implements dynamic output pin utilization where the same output pins are reused across multiple testing cycles and different memory banks. Instead of requiring dedicated output pins for each parallel test channel, the system dynamically allocates and reuses output resources, maintaining high parallel productivity while reducing the total number of physical output pins required.
Data Source
AI summary
A parallel bit test circuit for a semiconductor memory device may include a plurality of data compressors, a delay unit, and a bus width converter. The data compressors may receive data output from data lines, compress the data, and output the compressed data. The delay unit may receive a clock signal, and may generate (N−1) number of delayed clock signals from the clock signal when a burst length is a natural number equal to or more than 2. The bus width converter may receive the compressed data through M number of input terminals, divide the compressed data into N number of data sets, and serially output the N number of data sets through M/N number of output terminals in response to the clock signal and the (N−1) number of delayed clock signals, where M may be the number of bits of the data output from the data lines.