WAK Devices in SRAM Cells for Voltage Drop Isolation

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Solution Overview

Problem

In very small-scale integrated circuits, the reduced operation voltages and static noise lead to reduced read and write margins in SRAM cells, causing errors due to instantaneous voltage drops, which existing dual and single power schemes fail to adequately address.

Innovation Solution

The implementation of a memory circuit with a write-assist-keeper (WAK) device that switches between a primary power supply voltage and a secondary power supply voltage, lower than the primary, to improve read and write margins by isolating SRAM cells from instantaneous voltage drops, using a network of power supply lines and WAK devices distributed throughout the SRAM array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dynamic power supply voltages are used to improve read and write margins, then read and write margins are improved, but instantaneous voltage drops cause neighboring SRAM cells to lose stored bit values

Engineering Contradiction:

Improveread and write marginsVSAvoidstored bit values

Core Design Contradiction:

ReliabilityVSLoss of information

Solution Approach 1:

The patent divides the power supply system into multiple independent power supply lines, each serving specific SRAM cells. This segmentation allows different cells to experience different voltage levels during write operations, preventing the instantaneous voltage drop from propagating to neighboring cells and causing data loss.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces power supply lines as intermediaries between the power source and SRAM cells. These intermediate power supply lines act as buffers that isolate the instantaneous voltage drops, protecting neighboring cells from the full impact of voltage fluctuations during write operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Length of moving object

If operation voltage is reduced to enable smaller-scale integration, then device scaling is achieved, but read and write margins are reduced causing errors

Engineering Contradiction:

Improvedevice sizeVSAvoidread and write margins

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The patent applies different power supply voltages to different regions of the SRAM array. During write operations, neighboring cells receive a first power supply voltage optimized for write margin, while the cell being written receives a second (lower) power supply voltage. This local differentiation allows low-voltage operation for scaling while maintaining adequate margins through localized voltage optimization.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7733687B2WAK devices in SRAM cells for improving VCCMIN

Publication Date: 2010.06.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line.