Read Circuit Voltage Control for PRAM Speed and Margin
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Solution Overview
Problem
Resistance variable memory apparatuses face limitations in read operation speed and margin due to slow voltage level control during data retrieval in phase-change random access memory (PRAM) systems.
Innovation Solution
A read circuit that rapidly drops the voltage of a selected word line to a first ground voltage and boosts the voltage of a selected bit line to a power voltage, both for predetermined time periods, to quickly turn on the memory cell and enhance read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional voltage sensing or current sensing methods are used to read data in PRAM, then the read operation can be performed, but the read operation speed is slow and the read margin is limited due to slow voltage level control
Solution Approach 1:
The read circuit performs preliminary voltage level control by coupling the word line to a first ground voltage supply terminal for a preset first time period and the bit line to a power voltage supply terminal for a preset second time period before the selected resistance variable memory cell is fully turned on. This preliminary action prepares the voltage levels in advance, enabling faster read operation speed while maintaining sufficient read margin by ensuring proper voltage differential is established before current detection begins.
2Productivity
If the voltage level control is performed slowly during data retrieval, then the circuit has sufficient time to stabilize, but the read operation speed decreases
Solution Approach 1:
The read circuit employs periodic action by controlling the word line and bit line voltage levels for preset time periods before current detection. The word line is coupled to the first ground voltage supply terminal for a preset first time period, and the bit line is coupled to the power voltage supply terminal for a preset second time period. This time-controlled periodic voltage adjustment enables rapid voltage level establishment, significantly improving data retrieval efficiency while maintaining stability through predetermined timing intervals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly speeds up the read operation and improves the read margin by ensuring faster voltage level control, thereby enhancing the overall performance of the resistance variable memory apparatus.
Implementation Method 1
a logic level of the data bit may be determined based on an amount of current flowing through a memory cell turned on by a potential difference between both terminals of the memory cell
Data Source
AI summary
A resistance variable memory apparatus in accordance with an embodiment may include a memory cell array and a read circuit. The memory cell array may include a plurality of resistance variable memory cells coupled between a plurality of word lines and a plurality of bit lines. The read circuit may couple a word line, to which a selected resistance variable memory cell is coupled, to a first ground voltage supply terminal for a preset first time period before an amount of current flowing through the selected resistance variable memory cell is detected. The read circuit may couple a bit line, to which the selected resistance variable memory cell is coupled, to a power voltage supply terminal for a preset second time period, in a read operation.