Resistive Memory Read Circuit Precharge Sensing Margin
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Solution Overview
Problem
Semiconductor memory devices, particularly resistive memory devices, face performance degradation due to variations in manufacturing processes and signal variations, leading to slower read operations.
Innovation Solution
A memory device and system that includes a memory cell array, a read circuit, and control logic, where the read circuit precharges sensing and charge sharing nodes to different voltage levels, allowing the development of a voltage based on the resistance level of the memory cell, enabling efficient data reading through comparison with reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional read operation is used in resistive memory devices, then the device can read data, but the read operation time is long and sensing margin is insufficient
Solution Approach 1:
The patent applies preliminary action by precharging the sensing node and first node to different voltage levels before the actual read operation. This pre-charging step prepares the circuit in advance with optimized voltage conditions, enabling faster development of the voltage difference that reflects the memory cell state, thereby reducing read operation time while improving sensing margin.
2Ease of manufacture
If manufacturing process variations occur, then device fabrication is simplified, but performance degradation occurs due to signal variations
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting voltage levels applied to different nodes during the read operation. By changing voltage parameters (precharging sensing node to one level and first node to another level), the circuit compensates for manufacturing variations and signal fluctuations, maintaining stable performance across different device samples without requiring complex manufacturing controls.
3Device complexity
If read circuit uses simple voltage levels, then circuit complexity is reduced, but sensing precision is insufficient
Solution Approach 1:
The patent applies local quality by assigning different voltage levels to different nodes within the read circuit based on their specific functions. The sensing node receives one voltage level while the first node receives a different voltage level, optimizing each node's electrical characteristics for its specific role in detecting the memory cell state, thereby improving sensing precision without requiring overall circuit complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances read operation performance by increasing the sensing margin and reducing the read operation time, thereby improving the overall efficiency of data retrieval in resistive memory devices.
Implementation Method 1
a memory cell having a resistance level that varies depending on data stored therein
Implementation Method 2
develop a voltage of the sensing node based on the resistance level of the memory cell
Data Source
AI summary
A memory device includes a memory cell array, a read circuit, and a control logic. The memory cell array includes a memory cell having a resistance level that varies depending on data stored therein. The memory cell is connected to a first signal line and a second signal line. The read circuit is configured to read the data. The control logic is configured to precharge a sensing node, connected to the first signal line through a first switching device, and a first node, connected to the second signal line through a second switching device, to different voltage levels during a first period, and develop a voltage of the sensing node based on the resistance level of the memory cell during a second period.