3D Logic Base Die Layout for High-Bandwidth Memory Stacks
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high operating speeds and reducing manufacturing costs, particularly in the design of high-bandwidth memory devices where the integration of multiple dies and the separation of logic and memory functions complicate the base die structure.
Innovation Solution
A memory device architecture is proposed where a base die structure includes a first die with a three-dimensional logic transistor and a second die, separated from the first die, with a memory stack of dies stacked vertically. This configuration allows for improved signal transmission and data exchange through through-silicon vias, enhancing operating speed and reducing manufacturing costs by separating the logic and memory functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple dies are stacked vertically to increase memory capacity, then memory capacity is improved, but device complexity increases due to the need for through-silicon vias and complex interconnections
Solution Approach 1:
The base die is segmented into a first die and a second die that are separated from each other. The first die includes logic transistors while the second die includes memory transistors, allowing independent optimization of each die's function and reducing overall structural complexity
Solution Approach 2:
The patent transitions from a planar base die structure to a three-dimensional stacked structure with memory dies vertically stacked on the separated base dies, increasing memory capacity while managing complexity through vertical integration
2Device complexity
If logic and memory functions are integrated in a single base die, then device complexity is reduced, but operating speed decreases due to longer signal transmission paths
Solution Approach 1:
The base die is divided into separate first and second dies with distinct logic and memory functions, reducing signal transmission distances within each functional block and improving operating speed
Solution Approach 2:
Through-silicon vias serve as intermediary connection structures that enable high-speed vertical signal transmission between the stacked memory dies and the separated base dies, compensating for the segmentation of logic and memory functions
3Speed
If through-silicon vias are used to connect stacked memory dies, then operating speed is improved, but manufacturing cost increases
Solution Approach 1:
Separating the base die into first and second dies allows for optimized through-silicon via placement and reduced via density compared to a monolithic structure, potentially lowering manufacturing costs while maintaining high-speed performance
Solution Approach 2:
The separated base die structure enables localized optimization of through-silicon via distributions in different regions, allowing high-speed connections where needed while reducing manufacturing complexity in other areas
Data Source
AI summary
Disclosed is a memory device which includes a base die that includes a pair of second dies and a first die that is between the pair of second dies, and a memory stack that includes memory dies sequentially stacked on the base die in a vertical direction. The first die is electrically connected to the memory stack, and the first die includes a logic transistor including a channel of a three-dimensional structure.