3D Logic-Memory IC Structure with Monocrystalline Memory Channels
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Solution Overview
Problem
Wires in traditional two-dimensional integrated circuits (ICs) dominate performance, functionality, and power consumption, limiting further improvements in ICs, while existing 3D stacking techniques often use polysilicon for active memory cell channels, leading to higher cell-to-cell performance variations and lower drive.
Innovation Solution
The development of 3D IC devices with monocrystalline channels, utilizing oxide-to-oxide bonds and multiple metal layers, including structures such as metal gates, transistors, and memory arrays, to construct efficient 3D memory circuits with reduced construction costs and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If three-dimensional stacking is implemented to reduce wire lengths, then wiring delay is reduced, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional stacking of semiconductor layers, transitioning from traditional two-dimensional planar integration to vertical stacking. Multiple semiconductor layers are bonded together via through-silicon vias (TSVs) to form a 3D integrated structure, enabling transistors to be placed closer in the vertical dimension and significantly reducing wire lengths and wiring delay.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate semiconductor layers that can be independently fabricated and then bonded together. Each layer contains specific functional blocks (logic circuits, memory circuits, I/O circuits), allowing parallel fabrication and optimized interconnection through TSVs, thereby managing complexity through modular segmentation.
2Adaptability or versatility
If multiple semiconductor layers are bonded together to form 3D structure, then connectivity is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary fabrication of multiple semiconductor layers independently before bonding them together. Each layer is fully processed with transistors, interconnects, and functional circuits completed separately, allowing standard manufacturing processes to be used for each layer. The layers are then bonded using TSV technology with pre-formed via structures, reducing the complexity of in-situ 3D fabrication.
Solution Approach 2:
The patent uses through-silicon vias (TSVs) as intermediary structures to connect different semiconductor layers. TSVs provide vertical interconnect pathways through the bonded layers, enabling electrical connectivity between logic circuits in one layer and memory or I/O circuits in other layers without requiring complex direct bonding schemes.
3Speed
If through-silicon via technology is used to connect multiple layers, then wiring delay is reduced, but construction cost increases
Solution Approach 1:
The patent combines multiple functional circuits (logic, memory, I/O) into a single 3D integrated device using TSV technology. By merging these functions into one stacked structure rather than separate chips, the patent achieves high-speed inter-layer communication while consolidating manufacturing into a single device fabrication process, potentially reducing overall construction costs compared to multi-chip solutions.
Data Source
AI summary
A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.