3D Logic and Memory Stacking for Density Beyond 2D Scaling

The patent implements three-dimensional interconnect structures that route signals vertically through stacked layers rather than only laterally in planar layers. This vertical stacking of interconnect layers reduces the lateral wire pitch requirements and shortens signal path lengths, thereby decreasing resistance and capacitance while enabling higher wiring density for connecting increased transistor counts.

The patent employs nested interconnect structures where multiple conductive layers are stacked vertically with each layer nested within the vertical space of adjacent layers. This nested arrangement allows dense interconnection of vertically stacked transistors without increasing the lateral footprint, reducing wire length and improving electrical performance while maintaining high wiring density.

The patent divides the fabrication process into separate sequential stages: first forming a initial substrate with a set of transistors, then bonding a second substrate with additional transistors stacked vertically. This segmentation of the manufacturing process into discrete bondable modules allows each substrate to be fabricated using standard processes, with the 3D integration achieved through wafer bonding rather than attempting to form all layers in a single complex process.

The patent performs preliminary fabrication of complete transistor stacks on separate substrates before final assembly. Each substrate is fully processed with transistors, interconnects, and passivation layers completed in advance, then bonded together to form the 3D structure. This preliminary action on individual substrates simplifies the overall fabrication by avoiding the need to perform complex 3D structuring operations during the main fabrication sequence.