3D Logic-Memory Stack Using TSVs for Higher Chip Density
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Solution Overview
Problem
In existing semiconductor structures, the integration of logic devices and memory devices, such as FeRAM, in the same level of an integrated circuit structure leads to inefficient use of area, as memory devices consume valuable space that could be occupied by logic devices, hindering chip size scaling.
Innovation Solution
The semiconductor structure is designed with logic devices and memory devices formed in different levels of the integrated circuit, using a through-layer via to electrically connect them, allowing for a higher density of both logic and memory devices by separating their footprint, with faster SRAM devices at one level and slower FeRAM devices at another.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If logic devices and memory devices are formed in the same level of integrated circuit structure, then the fabrication process is simpler, but the area efficiency deteriorates because memory devices consume valuable space that could be occupied by logic devices
Solution Approach 1:
The patent transitions from a planar (2D) layout where logic and memory devices share the same level to a three-dimensional (3D) stacked architecture. Memory devices are formed in a first level while logic devices are formed in a second level above them, utilizing the vertical dimension to resolve the area efficiency problem while maintaining fabrication compatibility through sequential processing steps
2Device complexity
If memory devices are placed at the same level as logic devices, then routing connections are simpler, but the density of devices per unit area deteriorates
Solution Approach 1:
By stacking memory devices in a first level and logic devices in a second level, the patent achieves higher device density per unit area. Through-silicon vias (TSVs) and interconnect structures enable routing between levels, adding vertical connectivity paths that compensate for the increased routing complexity while significantly improving overall device density
Solution Approach 2:
The integrated circuit is segmented into distinct functional levels: a first level dedicated to memory devices and a second level dedicated to logic devices. This segmentation allows each level to be optimized independently for its specific function while maintaining overall system integration through vertical interconnects
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a first layer including a logic device, a second layer over the first layer including a first type memory device, and a though silicon via (TSV) electrically connecting the logic device and the first type memory device.