3D Lower Wiring Layout for Vertical Channel Memory Arrays
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Solution Overview
Problem
The development of memory devices with vertical channel transistors faces challenges in photolithography processes due to the complexity of forming minute patterns, which affects integration density and operational efficiency.
Innovation Solution
A semiconductor device design that includes a sense amplifier circuit, bit lines, gate electrodes, gate insulation patterns, channels made of oxide semiconductor material, upper contact plugs, and capacitors, with conductive structures between the sense amplifier circuit and bit lines, allowing for different levels of lower wirings to simplify the photolithography process and increase layout freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If photolithography process is used to form minute patterns for increased integration, then integration degree is improved, but process complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar 2D wiring to 3D multi-level wiring structures. Lower wirings are positioned at different vertical levels (first level and second level) beneath the bit lines, creating a three-dimensional arrangement that increases integration without requiring more complex photolithography patterns on the surface.
Solution Approach 2:
The wiring structure is segmented into multiple independent components: first lower contact plugs, first lower wirings at a first level, second lower contact plugs, and second lower wirings at a second level. This segmentation allows each component to be formed and connected independently, simplifying the overall manufacturing process while achieving high integration.
2Adaptability or versatility
If multiple lower wirings are arranged at the same level, then layout freedom is reduced, but if arranged at different levels, then manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension to arrange lower wirings at different levels. First lower wirings are positioned at a first vertical level while second lower wirings are positioned at a second vertical level, both beneath the bit lines. This 3D arrangement provides extensive layout freedom without increasing manufacturing complexity, as each level can be formed using standard multi-layer wiring techniques.
Data Source
AI summary
A semiconductor device includes a S/A circuit, bit lines, a gate electrode, a gate insulation pattern, a channel, an upper contact plug and a capacitor on a substrate. The bit lines includes first, second, third and fourth bit lines sequentially arranged in the second direction. A first lower contact plug, a first lower wiring and a second lower contact plug are sequentially stacked in a third direction between the S/A circuit and the first bit line, and are electrically connected to the S/A circuit and the first bit line. A third lower contact plug, a second lower wiring and a fourth lower contact plug are sequentially stacked in the third direction between the S/A circuit and the third bit line, and are electrically connected to the S/A circuit and the third bit line. The first and second lower wirings are at different levels from each other.