Capacitors TRIZ Cases
- 3D Lower Wiring Layout for Vertical Channel Memory Arrays
Multi-level lower wirings beneath bit lines ease photolithography, cut resistance, and improve vertical channel memory layout freedom.
- Doped Oxide Capacitor Structure Without Interface Oxide Layers
A doped metal-oxide lower electrode blocks natural interface oxide and depletion layers, improving DRAM capacitor electric characteristics.
- Multi-Oxide Capacitor Dielectric Structure for Leakage Suppression
A three-area metal oxide dielectric balances high capacitance with lower leakage current in miniaturized semiconductor capacitors.
- NC-FinFET Gate Stack Using Zirconium Oxide for Sub-60 Swing
Negative-capacitance zirconium oxide gate stacks cut subthreshold swing below 60 mV/decade, reduce leakage, and avoid annealing.
- HfO2-Seeded PZT Microsystem for Ferroelectric Fatigue Resistance
An HfO2 insulating film and PbTiO3 seed layer let planar-electrode PZT microsystems endure switching fatigue while keeping material flexibility.
- Capacitor Electrode Supporter Curvature for Misalignment Margin
Curved supporter sidewalls around adjacent lower electrodes increase misalignment margin and prevent bridging in dense semiconductor capacitors.
- Stacked Battery Module Fixing Structure With Fewer Connections
A spanning fixing member secures stacked household energy modules with fewer fixed joints, simplifying installation and maintenance.
- Stacked Ferroelectric Capacitor Structure for DRAM Capacitance Density
Alternating anti-ferroelectric and graded HfZrO2 ferroelectric layers help DRAM capacitors retain capacitance in shrinking unit cells.
- Composite Dielectric Capacitor Structure for Miniaturized Semiconductors
A dual-dielectric capacitor fills grain-boundary openings to raise dielectric constant and electrical reliability in miniaturized semiconductor structures.
- Semiconductor Contact Structure With Double Plug for Low-Resistance Stability
A double-plug contact structure improves semiconductor stability and lowers resistance while easing photo and etching limits.
- Capacitor Lower Electrode Liner Structure for BT Ratio Stability
A localized metal-nitride liner on the upper lower electrode improves BT ratio, prevents bending, and reduces leakage in scaled memory capacitors.
- Honeycomb Lower Electrode Support Structure to Prevent Contact
A honeycomb supporter with stress-relief holes and contoured sidewalls keeps dense lower electrodes separated and structurally stable.
- DRAM Capacitor Carbon Mold for Isotropic Core Removal
Using dense PECVD carbon as a removable DRAM capacitor mold enables isotropic core etching, simpler processing, and smaller cell sizes.
- Perovskite Capacitor Electrode Stack for Low-Leakage Memory Cells
Alternating metal-oxide lower electrode layers raise conduction band offset, cutting capacitor leakage and capacitance variation in dense memory cells.
- Photoresist Thickness Switching to Prevent Pattern Collapse
An etch-back step thins exposed photoresist before development, improving pattern distribution while preventing collapse and roughness.
- Ferroelectric Memory Interface Film for Uniform Orthorhombic Phase
An amorphous initiation layer guides uniform orthorhombic ferroelectric phase formation, preserving memory window consistency as FeRAM cells shrink.
- Capacitor Interfacial Film Structure for Higher Semiconductor Capacitance
Conductive interfacial films with higher-electronegativity metals reduce band offsets, raising semiconductor capacitor capacitance and refresh reliability.
- DRAM Capacitor Electrode Oxide Structure for High Capacitance, Low Stress
Doped oxide and metal oxide electrode layers raise DRAM capacitor capacitance while reducing stress in scaled memory structures.
- IC Module IO Pin Layout for Mixed Metal Scheme Integration
Oblique IO pins across metal layers give APR tools more routing freedom, easing IC module integration without layout revisions.
- High-k Capacitor Stack With Leakage-Blocking Interface Layers
A zirconium oxide capacitor stack uses titanium oxide and zirconium nitride interface layers to raise capacitance while suppressing leakage.
- DRAM Capacitor Interface Doping for Lower Leakage Current
A doped upper interface film deposited by ALD cuts DRAM capacitor leakage current while maintaining capacitance in high-density layouts.
- DRAM Capacitor Electrode Structure for Dense, Reliable Deposition
Segmented symmetric and asymmetric bottom electrodes widen deposition space, improving dielectric coverage and capacitor stability in dense DRAM fabrication.
- DRAM Capacitor Structure With Blocking Layer for Leakage Isolation
A high-bandgap blocking layer isolates the support and dielectric layers in DRAM capacitors to suppress leakage and preserve node separation.
- DRAM Capacitor Hole Structure for Perpendicular High-Aspect Etching
Progressive support and sacrificial layers keep high-aspect DRAM capacitor holes aligned, reducing etch deflection and stabilizing capacitor performance.
- Bottom-Electrode Interface Structure for FeRAM Leakage Control
A dielectric bottom-electrode interface blocks metal diffusion into the switching layer, cutting FeRAM leakage and improving data retention.