DRAM Capacitor Hole Structure for Perpendicular High-Aspect Etching
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Solution Overview
Problem
The challenge in forming high aspect ratio capacitor holes in DRAM devices is the tendency for etching to cause deflection, leading to non-perpendicularity, which affects the electrical properties and stability of the capacitor.
Innovation Solution
A method involving sequential formation of supporting and sacrificial layers, through holes, and filling structures to ensure perpendicularity, where the cross-sectional area of each hole is progressively increased to prevent collapse and improve etching alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the capacitor height is increased to achieve high aspect ratio, then the capacitor storage capacity per unit area is improved, but the etching perpendicularity of the capacitor hole deteriorates
Solution Approach 1:
The patent divides the capacitor formation process into multiple stages with sequential layer formation (first supporting layer, first sacrificial layer, second supporting layer, second sacrificial layer, third supporting layer). Each layer is formed with controlled thickness and patterned with progressively larger cross-sectional areas, segmenting the etching process into manageable steps that maintain perpendicularity while achieving high aspect ratio
Solution Approach 2:
The patent introduces progressive cross-sectional area expansion in the radial direction across multiple layers. Each subsequent layer has a larger cross-sectional area than the previous layer, creating a tapered structure that provides etching guidance and prevents deflection in the vertical dimension, thus solving the perpendicularity issue while maintaining high capacitor height
2Volume of moving object
If the capacitor hole aspect ratio is increased, then the capacitor storage capacity is improved, but the etching alignment and hole quality deteriorate due to deflection
Solution Approach 1:
The patent forms multiple supporting and sacrificial layers in advance before the final etching process. The first supporting layer and first sacrificial layer are formed and patterned first, followed by additional layers. This preliminary structuring creates a stable framework that guides subsequent etching operations, ensuring alignment accuracy even for high aspect ratio holes
Solution Approach 2:
The patent implements a nested multi-layer structure where the first supporting layer, first sacrificial layer, second supporting layer, second sacrificial layer, and third supporting layer are sequentially nested. Each layer is contained within and supported by the previous layers, creating a hierarchical structure that maintains structural integrity and alignment during the etching process
Data Source
AI summary
Method for forming a capacitor includes following operations. A base is provided. First supporting layer and first sacrificial layer are formed on the base sequentially. First through holes penetrating first supporting layer and first sacrificial layer are formed to expose the base. First through holes are filled to form first filling structures. Second supporting layer covering remaining first sacrificial layer and first filling structures is formed. Second through holes penetrating second supporting layer are formed. Second sacrificial layer covering remaining second supporting layer and second through holes, and third supporting layer are formed. Third through holes penetrating third supporting layer and second sacrificial layer are formed. First filling structures are removed to communicate each of third through holes and corresponding one of first through holes. First electrode layers, dielectric layer and second electrode layer covering first through holes and third through holes are formed sequentially to form the capacitor.