DRAM Capacitor Electrode Structure for Dense, Reliable Deposition

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Solution Overview

Problem

The challenge in semiconductor memory devices is to increase memory cell density while maintaining reliability and efficiency, particularly in DRAMs with recessed gate structures, where the complexity of fabricating processes and designs is heightened due to the need for high integration and high density.

Innovation Solution

The method involves forming sacrificial layers on the sidewalls of bottom electrode layers to create columnar structures with symmetric and asymmetric designs, which allows for enlarged distances between electrodes, facilitating the deposition of capacitor dielectric and top electrode layers, and forming supporting structures to stabilize the capacitor structure, thereby enhancing the reliability and performance of the semiconductor device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cell density is increased to meet high integration requirements, then storage capacity is improved, but the complexity of fabricating processes and designs increases

Engineering Contradiction:
Improvememory cell densityVSAvoidfabricating process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The bottom electrode layer is divided into multiple segments with different structures (first bottom electrode layer with symmetric columnar structure, second bottom electrode layer with asymmetric columnar structure). Each segment serves specific functions in the capacitor stack, allowing complex capacitor structures to be built through modular deposition processes rather than requiring monolithic complex electrode designs.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces horizontal extending portions that protrude from the vertical columnar structures of the bottom electrodes. This adds a horizontal dimension to the electrode geometry, creating overlapping regions that enhance capacitor reliability without increasing the vertical height or footprint of the memory cell, thus maintaining high density while improving performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If recessed gate structures are used to reduce leakage current, then reliability is improved, but the carrier channel length increases making fabrication more difficult

Engineering Contradiction:
Improveleakage current reductionVSAvoidfabrication difficulty
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The capacitor electrode structure is segmented into multiple layers (first bottom electrode layer, second bottom electrode layer, top electrode layer) with distinct geometric features. The first layer provides symmetric columnar support while the second layer adds asymmetric horizontal extending portions, creating a multi-functional electrode structure that simplifies the overall fabrication by breaking down complex capacitor formation into sequential, manageable deposition steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the bottom electrode structure have different geometries: the symmetric columnar portions provide vertical stability and alignment, while the asymmetric horizontal extending portions create localized overlapping regions with the capacitor dielectric. This local variation in electrode quality optimizes both structural support and capacitive coupling without uniformly increasing fabrication complexity across the entire device.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20230422481A1Semiconductor device and method of fabricating the same
Publication Date: 2023.12.28 FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
  • US20230422481A1 patent drawing
  • US20230422481A1 patent drawing
  • US20230422481A1 patent drawing

AI summary

The present disclosure provides a semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of storage node pads, a supporting structure, and a capacitor structure. The storage node pads are disposed on the substrate. The supporting structure is disposed on the substrate and includes a first supporting layer and a second supporting layer from bottom to top. The capacitor structure is disposed on the substrate, and the capacitor structure includes columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer stacked from bottom to top, wherein the columnar bottom electrodes include a first columnar bottom electrode having a symmetric columnar structure and a second columnar bottom electrode having an asymmetric columnar structure, and the first columnar bottom electrode and the second columnar bottom electrode respectively include at least one horizontal extending portion along a horizontal direction.